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Thumb assembly parsing and encoding for LDR(immediate) form T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -189,11 +189,13 @@ def t_addrmode_is1 : Operand<i32>,
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// t_addrmode_sp := sp + imm8 * 4
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//
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def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
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def t_addrmode_sp : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
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let EncoderMethod = "getAddrModeThumbSPOpValue";
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let DecoderMethod = "DecodeThumbAddrModeSP";
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let PrintMethod = "printThumbAddrModeSPOperand";
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let ParserMatchClass = t_addrmode_sp_asm_operand;
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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@ -626,7 +626,15 @@ public:
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// Immediate offset, multiple of 4 in range [0, 124].
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if (!Mem.OffsetImm) return true;
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int64_t Val = Mem.OffsetImm->getValue();
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return Val >= 0 && Val < 125 && (Val % 4) == 0;
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return Val >= 0 && Val <= 124 && (Val % 4) == 0;
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}
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bool isMemThumbSPI() const {
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if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
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return false;
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// Immediate offset, multiple of 4 in range [0, 1020].
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if (!Mem.OffsetImm) return true;
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int64_t Val = Mem.OffsetImm->getValue();
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return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
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}
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bool isMemImm8Offset() const {
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if (Kind != Memory || Mem.OffsetRegNum != 0)
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@ -992,6 +1000,13 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
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Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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@ -182,8 +182,15 @@ _func:
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ldr r1, [r5]
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ldr r2, [r6, #32]
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ldr r3, [r7, #124]
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ldr r1, [sp]
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ldr r2, [sp, #24]
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ldr r3, [sp, #1020]
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@ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68]
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@ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a]
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@ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f]
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@ CHECK: ldr r1, [sp] @ encoding: [0x00,0x99]
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@ CHECK: ldr r2, [sp, #24] @ encoding: [0x06,0x9a]
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@ CHECK: ldr r3, [sp, #1020] @ encoding: [0xff,0x9b]
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