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Compress SimpleValueType lists by sharing.
Many register classes have the same value types. Share the table space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -264,6 +264,10 @@ static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
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OS << getQualifiedName(Reg->TheDef);
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}
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static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
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OS << getEnumName(VT);
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}
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//
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// runMCDesc - Print out MC register descriptions.
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//
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@ -547,25 +551,14 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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AllocatableRegs.insert(Order.begin(), Order.end());
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}
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OS << "namespace { // Register classes...\n";
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// Emit the ValueType arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.getName() + "VTs";
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// Emit the register list now.
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OS << " // " << Name
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<< " Register Class Value Types...\n"
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<< " const MVT::SimpleValueType " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
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OS << getEnumName(RC.VTs[i]) << ", ";
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OS << "MVT::Other\n };\n\n";
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}
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OS << "} // end anonymous namespace\n\n";
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// Build a shared array of value types.
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SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
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VTSeqs.add(RegisterClasses[rc]->VTs);
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VTSeqs.layout();
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OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
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VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
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OS << "};\n";
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// Now that all of the structs have been emitted, emit the instances.
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if (!RegisterClasses.empty()) {
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@ -692,7 +685,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< RegisterClasses[i]->getName() << "RegClass = {\n "
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<< '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
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<< "RegClassID],\n "
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<< RC.getName() << "VTs,\n "
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<< "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
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<< RC.getName() << "SubclassMask,\n ";
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if (RC.getSuperClasses().empty())
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OS << "NullRegClasses,\n ";
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@ -103,7 +103,9 @@ public:
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/// emit - Print out the table as the body of an array initializer.
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/// Use the Print function to print elements.
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void emit(raw_ostream &OS, void (*Print)(raw_ostream&, ElemT)) const {
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void emit(raw_ostream &OS,
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void (*Print)(raw_ostream&, ElemT),
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const char *Term = "0") const {
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assert(Entries && "Call layout() before emit()");
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for (typename SeqMap::const_iterator I = Seqs.begin(), E = Seqs.end();
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I != E; ++I) {
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@ -113,7 +115,7 @@ public:
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Print(OS, *SI);
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OS << ", ";
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}
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OS << "0,\n";
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OS << Term << ",\n";
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}
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}
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};
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