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dont' call getX86RegNum on X86::RIP, it doesn't like that. This

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fixes the remaining x86-64 jit failures afaik.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95867 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-02-11 08:45:56 +00:00
parent 5526b69901
commit ecfb3c3d66
2 changed files with 7 additions and 3 deletions
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4
lib/Target/X86/X86CodeEmitter.cpp
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@ -387,7 +387,9 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
// If no BaseReg, issue a RIP relative instruction only if the MCE can // If no BaseReg, issue a RIP relative instruction only if the MCE can
// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
// 2-7) and absolute references. // 2-7) and absolute references.
unsigned BaseRegNo = BaseReg != 0 ? getX86RegNum(BaseReg) : -1U; unsigned BaseRegNo = -1U;
if (BaseReg != 0 && BaseReg != X86::RIP)
BaseRegNo = getX86RegNum(BaseReg);
if (// The SIB byte must be used if there is an index register. if (// The SIB byte must be used if there is an index register.
IndexReg.getReg() == 0 && IndexReg.getReg() == 0 &&

4
lib/Target/X86/X86MCCodeEmitter.cpp
View File

@ -175,7 +175,9 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
const MCOperand &Scale = MI.getOperand(Op+1); const MCOperand &Scale = MI.getOperand(Op+1);
const MCOperand &IndexReg = MI.getOperand(Op+2); const MCOperand &IndexReg = MI.getOperand(Op+2);
unsigned BaseReg = Base.getReg(); unsigned BaseReg = Base.getReg();
unsigned BaseRegNo = BaseReg != 0 ? GetX86RegNum(Base) : -1U; unsigned BaseRegNo = -1U;
if (BaseReg != 0 && BaseReg != X86::RIP)
BaseRegNo = GetX86RegNum(Base);
// Determine whether a SIB byte is needed. // Determine whether a SIB byte is needed.
// If no BaseReg, issue a RIP relative instruction only if the MCE can // If no BaseReg, issue a RIP relative instruction only if the MCE can