From ed00212f4359190df95c9970ac5b1e2fd2bda384 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 14:04:01 +0000
Subject: [PATCH] Implement asmprinting for odd-even regpairs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75974 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../SystemZ/AsmPrinter/SystemZAsmPrinter.cpp      | 15 +++++++++++++--
 lib/Target/SystemZ/SystemZInstrInfo.td            | 14 +++++++-------
 lib/Target/SystemZ/SystemZRegisterInfo.h          |  9 +++++++++
 3 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
index 8306e26b98c..f98d4ed7156 100644
--- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
+++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
@@ -181,11 +181,22 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                      const char* Modifier) {
   const MachineOperand &MO = MI->getOperand(OpNum);
   switch (MO.getType()) {
-  case MachineOperand::MO_Register:
+  case MachineOperand::MO_Register: {
     assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
             "Virtual registers should be already mapped!");
-    O << '%' << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+    unsigned Reg = MO.getReg();
+    if (Modifier && strncmp(Modifier, "subreg", 6) == 0) {
+      if (strncmp(Modifier + 7, "even", 4) == 0)
+        Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_EVEN);
+      else if (strncmp(Modifier + 7, "odd", 3) == 0)
+        Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_ODD);
+      else
+        assert(0 && "Invalid subreg modifier");
+    }
+
+    O << '%' << TRI->getAsmName(Reg);
     return;
+  }
   case MachineOperand::MO_Immediate:
     O << MO.getImm();
     return;
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 2c08c2fe601..6055b00eaa3 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -366,14 +366,14 @@ def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
                      "lgr\t{$dst, $src}",
                      []>;
 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
-                     "# MOV128 PSEUDO!"
-                     "lgr\t{$dst:subreg_odd, $src:subreg_odd}\n"
-                     "lgr\t{$dst:subreg_even, $src:subreg_even}",
+                     "# MOV128 PSEUDO!\n"
+                     "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
+                     "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
                      []>;
 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
-                     "# MOV64P PSEUDO!"
-                     "lr\t{$dst:subreg_odd, $src:subreg_odd}\n"
-                     "lr\t{$dst:subreg_even, $src:subreg_even}",
+                     "# MOV64P PSEUDO!\n"
+                     "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
+                     "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
                      []>;
 }
 
@@ -554,7 +554,7 @@ def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 
 // FIXME: Provide proper encoding!
 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
-                       "ahi\t{$dst, $src2:}",
+                       "ahi\t{$dst, $src2}",
                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
                         (implicit PSW)]>;
 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.h b/lib/Target/SystemZ/SystemZRegisterInfo.h
index d800f293989..9430c874636 100644
--- a/lib/Target/SystemZ/SystemZRegisterInfo.h
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.h
@@ -19,6 +19,15 @@
 
 namespace llvm {
 
+namespace SystemZ {
+  /// SubregIndex - The index of various sized subregister classes. Note that
+  /// these indices must be kept in sync with the class indices in the
+  /// SystemZRegisterInfo.td file.
+  enum SubregIndex {
+    SUBREG_32BIT = 1, SUBREG_EVEN = 1, SUBREG_ODD = 2
+  };
+}
+
 class SystemZSubtarget;
 class TargetInstrInfo;
 class Type;