6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 20:29:48 +00:00
Code Issues Projects Releases Wiki Activity

GVRequiresExtraLoad is now never used for calls, simplify it based on this.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-07-10 05:52:02 +00:00
parent 754b7650c2
commit ed0dca6a5d
6 changed files with 10 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -301,7 +301,7 @@ static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
!TM.getSubtarget<X86Subtarget>().isTargetDarwin())
return false;
return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM);
}
template<class CodeEmitter>

2
lib/Target/X86/X86FastISel.cpp
View File

@ -449,7 +449,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
// If the ABI doesn't require an extra load, return a direct reference to
// the global.
if (!Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
if (!Subtarget->GVRequiresExtraLoad(GV, TM)) {
if (Subtarget->isPICStyleRIPRel()) {
// Use rip-relative addressing if we can. Above we verified that the
// base and index registers are unused.

7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -4554,7 +4554,7 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
SelectionDAG &DAG) const {
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
bool ExtraLoadRequired =
Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
Subtarget->GVRequiresExtraLoad(GV, getTargetMachine());
// Create the TargetGlobalAddress node, folding in the constant
// offset if it is legal.
@ -7075,7 +7075,7 @@ bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
if (AM.BaseGV) {
// We can only fold this if we don't need an extra load.
if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine()))
return false;
// If BaseGV requires a register, we cannot also have a BaseReg.
if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine()) &&
@ -8841,8 +8841,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
}
// If we require an extra load to get this address, as in PIC mode, we
// can't accept it.
if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
false))
if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine()))
return;
if (hasMemory)

2
lib/Target/X86/X86InstrInfo.cpp
View File

@ -781,7 +781,7 @@ static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
/// isGVStub - Return true if the GV requires an extra load to get the
/// real address.
static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM);
}
/// CanRematLoadWithDispOperand - Return true if a load with the specified

11
lib/Target/X86/X86Subtarget.cpp
View File

@ -39,8 +39,7 @@ AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
/// value of GV itself. This means that the GlobalAddress must be in the base
/// or index register of the address, not the GV offset field.
bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
const TargetMachine &TM,
bool isDirectCall) const {
const TargetMachine &TM) const {
// Windows targets only require an extra load for DLLImport linkage values,
// and they need these regardless of whether we're in PIC mode or not.
if (isTargetCygMing() || isTargetWindows())
@ -51,8 +50,6 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
return false;
if (isTargetDarwin()) {
if (isDirectCall)
return false;
bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
if (GV->hasHiddenVisibility() &&
(Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
@ -60,11 +57,9 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
// target is x86-64 or the symbol is definitely defined in the current
// translation unit.
return false;
return !isDirectCall && (isDecl || GV->isWeakForLinker());
return isDecl || GV->isWeakForLinker();
} else if (isTargetELF()) {
// Extra load is needed for all externally visible.
if (isDirectCall)
return false;
if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
return false;
return true;
@ -77,7 +72,7 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
/// a register, but not an extra load.
bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
const TargetMachine &TM) const {
if (GVRequiresExtraLoad(GV, TM, false))
if (GVRequiresExtraLoad(GV, TM))
return true;
// Code below here need only consider cases where GVRequiresExtraLoad

3
lib/Target/X86/X86Subtarget.h
View File

@ -201,8 +201,7 @@ public:
/// symbols are indirect, loading the value at address GV rather then the
/// value of GV itself. This means that the GlobalAddress must be in the base
/// or index register of the address, not the GV offset field.
bool GVRequiresExtraLoad(const GlobalValue* GV, const TargetMachine &TM,
bool isDirectCall) const;
bool GVRequiresExtraLoad(const GlobalValue* GV, const TargetMachine &TM)const;
/// True if accessing the GV requires a register. This is a superset of the
/// cases where GVRequiresExtraLoad is true. Some variations of PIC require