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Don't put IT instruction before conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75361 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9,8 +9,8 @@
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#define DEBUG_TYPE "thumb2-it"
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#define DEBUG_TYPE "thumb2-it"
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#include "ARM.h"
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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@ -25,7 +25,7 @@ namespace {
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static char ID;
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static char ID;
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Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
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Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
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const ARMBaseInstrInfo *TII;
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const Thumb2InstrInfo *TII;
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ARMFunctionInfo *AFI;
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ARMFunctionInfo *AFI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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@ -40,13 +40,21 @@ namespace {
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char Thumb2ITBlockPass::ID = 0;
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char Thumb2ITBlockPass::ID = 0;
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}
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}
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ARMCC::CondCodes getPredicate(const MachineInstr *MI,
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const Thumb2InstrInfo *TII) {
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unsigned Opc = MI->getOpcode();
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if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
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return ARMCC::AL;
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return TII->getPredicate(MI);
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}
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bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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bool Modified = false;
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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while (MBBI != E) {
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MachineInstr *MI = &*MBBI;
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MachineInstr *MI = &*MBBI;
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ARMCC::CondCodes CC = TII->getPredicate(MI);
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ARMCC::CondCodes CC = getPredicate(MI, TII);
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if (CC == ARMCC::AL) {
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if (CC == ARMCC::AL) {
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++MBBI;
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++MBBI;
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continue;
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continue;
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@ -64,7 +72,7 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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unsigned Mask = 0x8;
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unsigned Mask = 0x8;
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while (MBBI != E || (Mask & 1)) {
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while (MBBI != E || (Mask & 1)) {
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ARMCC::CondCodes NCC = TII->getPredicate(&*MBBI);
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ARMCC::CondCodes NCC = getPredicate(&*MBBI, TII);
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if (NCC == CC) {
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if (NCC == CC) {
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Mask >>= 1;
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Mask >>= 1;
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Mask |= 0x8;
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Mask |= 0x8;
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@ -86,7 +94,7 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
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bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
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bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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const TargetMachine &TM = Fn.getTarget();
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AFI = Fn.getInfo<ARMFunctionInfo>();
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AFI = Fn.getInfo<ARMFunctionInfo>();
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TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
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TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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if (!AFI->isThumbFunction())
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if (!AFI->isThumbFunction())
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return false;
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return false;
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19
test/CodeGen/Thumb2/thumb2-bcc.ll
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19
test/CodeGen/Thumb2/thumb2-bcc.ll
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@ -0,0 +1,19 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | not grep it
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define i32 @t1(i32 %a, i32 %b, i32 %c) {
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; CHECK: t1
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; CHECK: beq
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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%tmp6 = and i32 %tmp5, %c
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ret i32 %tmp6
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cond_false:
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%tmp7 = add i32 %b, -1
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%tmp8 = xor i32 %tmp7, %c
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ret i32 %tmp8
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}
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