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Autogen subtarget information from .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23904 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,46 +16,22 @@
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/SubtargetFeature.h"
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#include "llvm/Support/Debug.h"
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#include "AlphaGenSubtarget.inc"
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using namespace llvm;
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enum AlphaFeature {
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AlphaFeatureCIX = 1 << 0,
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AlphaFeatureFIX = 1 << 1,
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enum {
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FeatureKVSize = sizeof(FeatureKV) / sizeof(SubtargetFeatureKV),
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SubTypeKVSize = sizeof(SubTypeKV) / sizeof(SubtargetFeatureKV)
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};
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/// Sorted (by key) array of values for CPU subtype.
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static const SubtargetFeatureKV AlphaSubTypeKV[] = {
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{ "ev56" , "Select the Alpha EV56 processor", 0 },
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{ "ev6" , "Select the Alpha EV6 processor", AlphaFeatureFIX },
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{ "ev67" , "Select the Alpha EV67 processor", AlphaFeatureFIX | AlphaFeatureCIX },
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{ "generic", "Select instructions for a generic Alpha processor (EV56)", 0 },
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{ "pca56" , "Select the Alpha PCA56 processor", 0 },
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};
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/// Length of AlphaSubTypeKV.
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static const unsigned AlphaSubTypeKVSize = sizeof(AlphaSubTypeKV)
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/ sizeof(SubtargetFeatureKV);
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/// Sorted (by key) array of values for CPU features.
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static SubtargetFeatureKV AlphaFeatureKV[] = {
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{ "CIX", "Should CIX extentions be used" , AlphaFeatureCIX },
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{ "FIX" , "Should FIX extentions be used" , AlphaFeatureFIX },
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};
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/// Length of AlphaFeatureKV.
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static const unsigned AlphaFeatureKVSize = sizeof(AlphaFeatureKV)
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/ sizeof(SubtargetFeatureKV);
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AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS)
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:HasF2I(false), HasCT(false)
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{
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: HasF2I(false), HasCT(false) {
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std::string CPU = "generic";
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uint32_t Bits =
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SubtargetFeatures::Parse(FS, CPU,
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AlphaSubTypeKV, AlphaSubTypeKVSize,
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AlphaFeatureKV, AlphaFeatureKVSize);
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HasF2I = (Bits & AlphaFeatureFIX) != 0;
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HasCT = (Bits & AlphaFeatureCIX) != 0;
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SubtargetFeatures::Parse(FS, CPU,
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SubTypeKV, SubTypeKVSize,
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FeatureKV, FeatureKVSize);
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HasF2I = (Bits & FeatureFIX) != 0;
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HasCT = (Bits & FeatureCIX) != 0;
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}
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@ -14,6 +14,7 @@ TARGET = Alpha
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BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
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AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
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AlphaGenInstrInfo.inc AlphaGenCodeEmitter.inc \
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AlphaGenAsmWriter.inc AlphaGenDAGISel.inc
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AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
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AlphaGenSubtarget.inc
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include $(LEVEL)/Makefile.common
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