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Mark mayLoad, mayStore for insns correctly and use them
to check if an insn is accessing memory during mem sel optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71537 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,25 +64,7 @@ public:
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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static inline bool hasNoMemOperand (const MachineInstr &MI) {
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if (MI.getNumOperands() == 0) return true;
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switch (MI.getOpcode()) {
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default: return false; // Beware
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case PIC16::movlw_lo_1:
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case PIC16::movlw_hi_1:
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case PIC16::movlw_lo_2:
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case PIC16::movlw_hi_2:
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return true;
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}
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}
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};
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};
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} // namespace llvm
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#endif
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@ -132,7 +132,7 @@ include "PIC16InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// W = W Op F : Load the value from F and do Op to W.
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let isTwoAddress = 1 in
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let isTwoAddress = 1, mayLoad = 1 in
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class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -145,6 +145,7 @@ class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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// This insn class is not marked as TwoAddress because the reg is
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// being used as a source operand only. (Remember a TwoAddress insn
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// needs a copyRegToReg.)
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let mayStore = 1 in
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class BinOpWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -266,6 +267,7 @@ def restore_fsr1: RESTORE_FSR<"restore_fsr1">;
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// Direct store.
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// Input operands are: val = W, ptrlo = GA, offset = offset, ptrhi = banksel.
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let mayStore = 1 in
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class MOVWF_INSN<bits<6> OpCode, SDNode OpNodeDest, SDNode Op>:
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ByteFormat<0, (outs),
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(ins GPR:$val, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -297,6 +299,7 @@ def store_indirect :
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// Direct load.
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// Input Operands are: ptrlo = GA, offset = offset, ptrhi = banksel.
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// Output: dst = W
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let mayLoad = 1 in
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class MOVF_INSN<bits<6> OpCode, SDNode OpNodeSrc, SDNode Op>:
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ByteFormat<0, (outs GPR:$dst),
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(ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -357,7 +360,7 @@ def addwfc: BinOpWF<0, "addwfc", adde>; // With Carry.
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}
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// W -= [F] ; load from F and sub the value from W.
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let isTwoAddress = 1 in
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let isTwoAddress = 1, mayLoad = 1 in
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class SUBFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -376,6 +379,7 @@ def subfw_cc: SUBFW<0, "subwf", PIC16Subcc>;
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}
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// [F] -= W ;
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let mayStore = 1 in
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class SUBWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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@ -104,9 +104,13 @@ bool MemSelOpt::processInstruction(MachineInstr *MI) {
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bool Changed = false;
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unsigned NumOperands = MI->getNumOperands();
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// If this insn has only one operand, probably it is not going to
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// access any data memory.
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if (PIC16InstrInfo::hasNoMemOperand(*MI)) return Changed;
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if (NumOperands == 0) return false;
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// If this insn is not going to access any memory, return.
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const TargetInstrDesc &TID = TII->get(MI->getOpcode());
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if (! (TID.isCall() || TID.mayLoad() || TID.mayStore()))
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return false;
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// Scan for the memory address operand.
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// FIXME: Should we use standard interfaces like memoperands_iterator,
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