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Mark mayLoad, mayStore for insns correctly and use them

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to check if an insn is accessing memory during mem sel optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjiv Gupta 2009-05-12 04:30:38 +00:00
parent 74b0ccc577
commit ed4f4fbfba
3 changed files with 14 additions and 24 deletions
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20
lib/Target/PIC16/PIC16InstrInfo.h
View File

@ -64,25 +64,7 @@ public:
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
static inline bool hasNoMemOperand (const MachineInstr &MI) {
if (MI.getNumOperands() == 0) return true;
switch (MI.getOpcode()) {
default: return false; // Beware
case PIC16::movlw_lo_1:
case PIC16::movlw_hi_1:
case PIC16::movlw_lo_2:
case PIC16::movlw_hi_2:
return true;
}
}
};
};
} // namespace llvm
#endif

8
lib/Target/PIC16/PIC16InstrInfo.td
View File

@ -132,7 +132,7 @@ include "PIC16InstrFormats.td"
//===----------------------------------------------------------------------===//
// W = W Op F : Load the value from F and do Op to W.
let isTwoAddress = 1 in
let isTwoAddress = 1, mayLoad = 1 in
class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
ByteFormat<OpCode, (outs GPR:$dst),
(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
@ -145,6 +145,7 @@ class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
// This insn class is not marked as TwoAddress because the reg is
// being used as a source operand only. (Remember a TwoAddress insn
// needs a copyRegToReg.)
let mayStore = 1 in
class BinOpWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
ByteFormat<OpCode, (outs),
(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
@ -266,6 +267,7 @@ def restore_fsr1: RESTORE_FSR<"restore_fsr1">;
// Direct store.
// Input operands are: val = W, ptrlo = GA, offset = offset, ptrhi = banksel.
let mayStore = 1 in
class MOVWF_INSN<bits<6> OpCode, SDNode OpNodeDest, SDNode Op>:
ByteFormat<0, (outs),
(ins GPR:$val, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
@ -297,6 +299,7 @@ def store_indirect :
// Direct load.
// Input Operands are: ptrlo = GA, offset = offset, ptrhi = banksel.
// Output: dst = W
let mayLoad = 1 in
class MOVF_INSN<bits<6> OpCode, SDNode OpNodeSrc, SDNode Op>:
ByteFormat<0, (outs GPR:$dst),
(ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
@ -357,7 +360,7 @@ def addwfc: BinOpWF<0, "addwfc", adde>; // With Carry.
}
// W -= [F] ; load from F and sub the value from W.
let isTwoAddress = 1 in
let isTwoAddress = 1, mayLoad = 1 in
class SUBFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
ByteFormat<OpCode, (outs GPR:$dst),
(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
@ -376,6 +379,7 @@ def subfw_cc: SUBFW<0, "subwf", PIC16Subcc>;
}
// [F] -= W ;
let mayStore = 1 in
class SUBWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
ByteFormat<OpCode, (outs),
(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),

10
lib/Target/PIC16/PIC16MemSelOpt.cpp
View File

@ -104,9 +104,13 @@ bool MemSelOpt::processInstruction(MachineInstr *MI) {
bool Changed = false;
unsigned NumOperands = MI->getNumOperands();
// If this insn has only one operand, probably it is not going to
// access any data memory.
if (PIC16InstrInfo::hasNoMemOperand(*MI)) return Changed;
if (NumOperands == 0) return false;
// If this insn is not going to access any memory, return.
const TargetInstrDesc &TID = TII->get(MI->getOpcode());
if (! (TID.isCall() || TID.mayLoad() || TID.mayStore()))
return false;
// Scan for the memory address operand.
// FIXME: Should we use standard interfaces like memoperands_iterator,