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DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents.

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This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents.  The included change
fixes the PowerPC tests, and was OK'd by Hal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180129 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2013-04-23 18:09:28 +00:00
parent 3579a29dba
commit ed5707baf9
2 changed files with 4 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4451,7 +4451,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::SETCC) {
// sext(setcc) -> sext_in_reg(vsetcc) for vectors.
// Only do this before legalize for now.
if (VT.isVector() && !LegalOperations) {
if (VT.isVector() && !LegalOperations &&
TLI.getBooleanContents(true) ==
TargetLowering::ZeroOrNegativeOneBooleanContent) {
EVT N0VT = N0.getOperand(0).getValueType();
// On some architectures (such as SSE/NEON/etc) the SETCC result type is
// of the same size as the compared operands. Only optimize sext(setcc())

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -514,7 +514,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // FIXME: Is this correct?
if (isPPC64) {
setStackPointerRegisterToSaveRestore(PPC::X1);