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forward() should not increment internal iterator. Its client may insert instruction between now and next forward() call.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-02-27 01:58:48 +00:00
parent 30f44f3287
commit ed570dedad
3 changed files with 32 additions and 5 deletions
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29
lib/CodeGen/RegisterScavenging.cpp
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@@ -22,10 +22,11 @@
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
RegScavenger::RegScavenger(MachineBasicBlock *mbb)
: MBB(mbb), MBBI(mbb->begin()) {
: MBB(mbb), MBBIInited(false) {
const MachineFunction &MF = *MBB->getParent();
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo *RegInfo = TM.getRegisterInfo();
@@ -52,6 +53,14 @@ RegScavenger::RegScavenger(MachineBasicBlock *mbb)
}
void RegScavenger::forward() {
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
// Move ptr forward.
if (!MBBIInited) {
MBBI = MBB->begin();
MBBIInited = true;
} else
MBBI = next(MBBI);
MachineInstr *MI = MBBI;
// Process uses first.
BitVector ChangedRegs(NumPhysRegs);
@@ -86,12 +95,14 @@ void RegScavenger::forward() {
if (!MO.isDead())
setUsed(Reg);
}
++MBBI;
}
void RegScavenger::backward() {
MachineInstr *MI = --MBBI;
assert(MBBI != MBB->begin() && "Already at start of basic block!");
// Move ptr backward.
MBBI = prior(MBBI);
MachineInstr *MI = MBBI;
// Process defs first.
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -122,6 +133,16 @@ void RegScavenger::backward() {
setUsed(ChangedRegs);
}
void RegScavenger::forward(MachineBasicBlock::iterator I) {
while (MBBI != I)
forward();
}
void RegScavenger::backward(MachineBasicBlock::iterator I) {
while (MBBI != I)
backward();
}
/// CreateRegClassMask - Set the bits that represent the registers in the
/// TargetRegisterClass.
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {