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Change TargetParser enum names to avoid macro conflicts (llvm)

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sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1"
using a cpp macro.  The result is that this fails to compile.

Fixes https://llvm.org/PR23482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237112 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2015-05-12 10:33:58 +00:00
parent 3bf2f23adb
commit ed73167673
5 changed files with 173 additions and 173 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
include/llvm/Support/TargetParser.h
View File

@ -27,64 +27,64 @@ namespace llvm {
namespace ARM {
// FPU names.
enum FPUKind {
INVALID_FPU = 0,
VFP,
VFPV2,
VFPV3,
VFPV3_D16,
VFPV4,
VFPV4_D16,
FPV5_D16,
FP_ARMV8,
NEON,
NEON_VFPV4,
NEON_FP_ARMV8,
CRYPTO_NEON_FP_ARMV8,
SOFTVFP,
LAST_FPU
FK_INVALID = 0,
FK_VFP,
FK_VFPV2,
FK_VFPV3,
FK_VFPV3_D16,
FK_VFPV4,
FK_VFPV4_D16,
FK_FPV5_D16,
FK_FP_ARMV8,
FK_NEON,
FK_NEON_VFPV4,
FK_NEON_FP_ARMV8,
FK_CRYPTO_NEON_FP_ARMV8,
FK_SOFTVFP,
FK_LAST
};
// Arch names.
enum ArchKind {
INVALID_ARCH = 0,
ARMV2,
ARMV2A,
ARMV3,
ARMV3M,
ARMV4,
ARMV4T,
ARMV5,
ARMV5T,
ARMV5TE,
ARMV6,
ARMV6J,
ARMV6K,
ARMV6T2,
ARMV6Z,
ARMV6ZK,
ARMV6M,
ARMV7,
ARMV7A,
ARMV7R,
ARMV7M,
ARMV8A,
ARMV8_1A,
IWMMXT,
IWMMXT2,
LAST_ARCH
AK_INVALID = 0,
AK_ARMV2,
AK_ARMV2A,
AK_ARMV3,
AK_ARMV3M,
AK_ARMV4,
AK_ARMV4T,
AK_ARMV5,
AK_ARMV5T,
AK_ARMV5TE,
AK_ARMV6,
AK_ARMV6J,
AK_ARMV6K,
AK_ARMV6T2,
AK_ARMV6Z,
AK_ARMV6ZK,
AK_ARMV6M,
AK_ARMV7,
AK_ARMV7A,
AK_ARMV7R,
AK_ARMV7M,
AK_ARMV8A,
AK_ARMV8_1A,
AK_IWMMXT,
AK_IWMMXT2,
AK_LAST
};
// Arch extension modifiers for CPUs.
enum ArchExtKind {
INVALID_ARCHEXT = 0,
CRC,
CRYPTO,
FP,
HWDIV,
MP,
SEC,
VIRT,
LAST_ARCHEXT
AEK_INVALID = 0,
AEK_CRC,
AEK_CRYPTO,
AEK_FP,
AEK_HWDIV,
AEK_MP,
AEK_SEC,
AEK_VIRT,
AEK_LAST
};
} // namespace ARM

110
lib/Support/TargetParser.cpp
View File

@ -27,20 +27,20 @@ struct {
const char * Name;
ARM::FPUKind ID;
} FPUNames[] = {
{ "invalid", ARM::INVALID_FPU },
{ "vfp", ARM::VFP },
{ "vfpv2", ARM::VFPV2 },
{ "vfpv3", ARM::VFPV3 },
{ "vfpv3-d16", ARM::VFPV3_D16 },
{ "vfpv4", ARM::VFPV4 },
{ "vfpv4-d16", ARM::VFPV4_D16 },
{ "fpv5-d16", ARM::FPV5_D16 },
{ "fp-armv8", ARM::FP_ARMV8 },
{ "neon", ARM::NEON },
{ "neon-vfpv4", ARM::NEON_VFPV4 },
{ "neon-fp-armv8", ARM::NEON_FP_ARMV8 },
{ "crypto-neon-fp-armv8", ARM::CRYPTO_NEON_FP_ARMV8 },
{ "softvfp", ARM::SOFTVFP }
{ "invalid", ARM::FK_INVALID },
{ "vfp", ARM::FK_VFP },
{ "vfpv2", ARM::FK_VFPV2 },
{ "vfpv3", ARM::FK_VFPV3 },
{ "vfpv3-d16", ARM::FK_VFPV3_D16 },
{ "vfpv4", ARM::FK_VFPV4 },
{ "vfpv4-d16", ARM::FK_VFPV4_D16 },
{ "fpv5-d16", ARM::FK_FPV5_D16 },
{ "fp-armv8", ARM::FK_FP_ARMV8 },
{ "neon", ARM::FK_NEON },
{ "neon-vfpv4", ARM::FK_NEON_VFPV4 },
{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 },
{ "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
{ "softvfp", ARM::FK_SOFTVFP }
};
// List of canonical arch names (use getArchSynonym)
// FIXME: TableGen this.
@ -50,31 +50,31 @@ struct {
const char *DefaultCPU;
ARMBuildAttrs::CPUArch DefaultArch;
} ARCHNames[] = {
{ "invalid", ARM::INVALID_ARCH, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
{ "armv2", ARM::ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
{ "armv2a", ARM::ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
{ "armv3", ARM::ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
{ "armv3m", ARM::ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
{ "armv4", ARM::ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
{ "armv4t", ARM::ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
{ "armv5", ARM::ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
{ "armv5t", ARM::ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
{ "armv5te", ARM::ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
{ "armv6", ARM::ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
{ "armv6j", ARM::ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
{ "armv6k", ARM::ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
{ "armv6t2", ARM::ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
{ "armv6z", ARM::ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6zk", ARM::ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6-m", ARM::ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
{ "armv7", ARM::ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-a", ARM::ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-r", ARM::ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-m", ARM::ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
{ "armv8-a", ARM::ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
{ "armv8.1-a", ARM::ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
{ "iwmmxt", ARM::IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
{ "iwmmxt2", ARM::IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
{ "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
{ "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
{ "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
{ "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
{ "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
{ "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
{ "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
{ "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
{ "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
{ "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
{ "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
{ "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
{ "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
{ "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
{ "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
{ "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
{ "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
};
// List of canonical ARCH names (use getARCHSynonym)
// FIXME: TableGen this.
@ -82,14 +82,14 @@ struct {
const char *Name;
ARM::ArchExtKind ID;
} ARCHExtNames[] = {
{ "invalid", ARM::INVALID_ARCHEXT },
{ "crc", ARM::CRC },
{ "crypto", ARM::CRYPTO },
{ "fp", ARM::FP },
{ "idiv", ARM::HWDIV },
{ "mp", ARM::MP },
{ "sec", ARM::SEC },
{ "virt", ARM::VIRT }
{ "invalid", ARM::AEK_INVALID },
{ "crc", ARM::AEK_CRC },
{ "crypto", ARM::AEK_CRYPTO },
{ "fp", ARM::AEK_FP },
{ "idiv", ARM::AEK_HWDIV },
{ "mp", ARM::AEK_MP },
{ "sec", ARM::AEK_SEC },
{ "virt", ARM::AEK_VIRT }
};
} // namespace
@ -101,31 +101,31 @@ namespace llvm {
// ======================================================= //
const char *ARMTargetParser::getFPUName(unsigned ID) {
if (ID >= ARM::LAST_FPU)
if (ID >= ARM::FK_LAST)
return nullptr;
return FPUNames[ID].Name;
}
const char *ARMTargetParser::getArchName(unsigned ID) {
if (ID >= ARM::LAST_ARCH)
if (ID >= ARM::AK_LAST)
return nullptr;
return ARCHNames[ID].Name;
}
const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) {
if (ID >= ARM::LAST_ARCH)
if (ID >= ARM::AK_LAST)
return nullptr;
return ARCHNames[ID].DefaultCPU;
}
unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) {
if (ID >= ARM::LAST_ARCH)
if (ID >= ARM::AK_LAST)
return 0;
return ARCHNames[ID].DefaultArch;
}
const char *ARMTargetParser::getArchExtName(unsigned ID) {
if (ID >= ARM::LAST_ARCHEXT)
if (ID >= ARM::AEK_LAST)
return nullptr;
return ARCHExtNames[ID].Name;
}
@ -170,7 +170,7 @@ unsigned ARMTargetParser::parseFPU(StringRef FPU) {
if (Syn == F.Name)
return F.ID;
}
return ARM::INVALID_FPU;
return ARM::FK_INVALID;
}
unsigned ARMTargetParser::parseArch(StringRef Arch) {
@ -179,7 +179,7 @@ unsigned ARMTargetParser::parseArch(StringRef Arch) {
if (Syn == A.Name)
return A.ID;
}
return ARM::INVALID_ARCH;
return ARM::AK_INVALID;
}
unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
@ -187,7 +187,7 @@ unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
if (ArchExt == A.Name)
return A.ID;
}
return ARM::INVALID_ARCHEXT;
return ARM::AEK_INVALID;
}
} // namespace llvm

18
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -591,7 +591,7 @@ void ARMAsmPrinter::emitAttributes() {
// We consider krait as a "cortex-a9" + hwdiv CPU
// Enable hwdiv through ".arch_extension idiv"
if (STI.hasDivide() || STI.hasDivideInARMMode())
ATS.emitArchExtension(ARM::HWDIV);
ATS.emitArchExtension(ARM::AEK_HWDIV);
} else
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
}
@ -628,13 +628,13 @@ void ARMAsmPrinter::emitAttributes() {
* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
if (STI.hasFPARMv8()) {
if (STI.hasCrypto())
ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
else
ATS.emitFPU(ARM::NEON_FP_ARMV8);
ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
} else if (STI.hasVFP4())
ATS.emitFPU(ARM::NEON_VFPV4);
ATS.emitFPU(ARM::FK_NEON_VFPV4);
else
ATS.emitFPU(ARM::NEON);
ATS.emitFPU(ARM::FK_NEON);
// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
if (STI.hasV8Ops())
ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
@ -644,13 +644,13 @@ void ARMAsmPrinter::emitAttributes() {
if (STI.hasFPARMv8())
// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
// FPU, but there are two different names for it depending on the CPU.
ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
ATS.emitFPU(STI.hasD16() ? ARM::FK_FPV5_D16 : ARM::FK_FP_ARMV8);
else if (STI.hasVFP4())
ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV4_D16 : ARM::FK_VFPV4);
else if (STI.hasVFP3())
ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
else if (STI.hasVFP2())
ATS.emitFPU(ARM::VFPV2);
ATS.emitFPU(ARM::FK_VFPV2);
}
if (TM.getRelocationModel() == Reloc::PIC_) {

32
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -9041,7 +9041,7 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
unsigned ID = ARMTargetParser::parseArch(Arch);
if (ID == ARM::INVALID_ARCH) {
if (ID == ARM::AK_INVALID) {
Error(L, "Unknown arch name");
return false;
}
@ -9190,49 +9190,49 @@ static const struct {
const uint64_t Enabled;
const uint64_t Disabled;
} FPUs[] = {
{/* ID */ ARM::VFP,
{/* ID */ ARM::FK_VFP,
/* Enabled */ ARM::FeatureVFP2,
/* Disabled */ ARM::FeatureNEON},
{/* ID */ ARM::VFPV2,
{/* ID */ ARM::FK_VFPV2,
/* Enabled */ ARM::FeatureVFP2,
/* Disabled */ ARM::FeatureNEON},
{/* ID */ ARM::VFPV3,
{/* ID */ ARM::FK_VFPV3,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
{/* ID */ ARM::VFPV3_D16,
{/* ID */ ARM::FK_VFPV3_D16,
/* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
/* Disabled */ ARM::FeatureNEON},
{/* ID */ ARM::VFPV4,
{/* ID */ ARM::FK_VFPV4,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
{/* ID */ ARM::VFPV4_D16,
{/* ID */ ARM::FK_VFPV4_D16,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureD16,
/* Disabled */ ARM::FeatureNEON},
{/* ID */ ARM::FPV5_D16,
{/* ID */ ARM::FK_FPV5_D16,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureFPARMv8 | ARM::FeatureD16,
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
{/* ID */ ARM::FP_ARMV8,
{/* ID */ ARM::FK_FP_ARMV8,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureFPARMv8,
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
{/* ID */ ARM::NEON,
{/* ID */ ARM::FK_NEON,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
/* Disabled */ ARM::FeatureD16},
{/* ID */ ARM::NEON_VFPV4,
{/* ID */ ARM::FK_NEON_VFPV4,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureNEON,
/* Disabled */ ARM::FeatureD16},
{/* ID */ ARM::NEON_FP_ARMV8,
{/* ID */ ARM::FK_NEON_FP_ARMV8,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureFPARMv8 | ARM::FeatureNEON,
/* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
{/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
{/* ID */ ARM::FK_CRYPTO_NEON_FP_ARMV8,
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
/* Disabled */ ARM::FeatureD16},
{ARM::SOFTVFP, 0, 0},
{ARM::FK_SOFTVFP, 0, 0},
};
/// parseDirectiveFPU
@ -9243,7 +9243,7 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
unsigned ID = ARMTargetParser::parseFPU(FPU);
if (ID == ARM::INVALID_FPU) {
if (ID == ARM::FK_INVALID) {
Error(FPUNameLoc, "Unknown FPU name");
return false;
}
@ -9897,7 +9897,7 @@ bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
unsigned ID = ARMTargetParser::parseArch(Arch);
if (ID == ARM::INVALID_ARCH) {
if (ID == ARM::AK_INVALID) {
Error(ArchLoc, "unknown architecture '" + Arch + "'");
Parser.eatToEndOfStatement();
return false;

86
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -386,8 +386,8 @@ private:
public:
ARMTargetELFStreamer(MCStreamer &S)
: ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
Arch(ARM::INVALID_ARCH), EmittedArch(ARM::INVALID_ARCH),
: ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID),
Arch(ARM::AK_INVALID), EmittedArch(ARM::AK_INVALID),
AttributeSection(nullptr) {}
};
@ -692,7 +692,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
ARMTargetParser::getArchDefaultCPUName(Arch),
false);
if (EmittedArch == ARM::INVALID_ARCH)
if (EmittedArch == ARM::AK_INVALID)
setAttributeItem(CPU_arch,
ARMTargetParser::getArchDefaultCPUArch(Arch),
false);
@ -702,64 +702,64 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
false);
switch (Arch) {
case ARM::ARMV2:
case ARM::ARMV2A:
case ARM::ARMV3:
case ARM::ARMV3M:
case ARM::ARMV4:
case ARM::ARMV5:
case ARM::AK_ARMV2:
case ARM::AK_ARMV2A:
case ARM::AK_ARMV3:
case ARM::AK_ARMV3M:
case ARM::AK_ARMV4:
case ARM::AK_ARMV5:
setAttributeItem(ARM_ISA_use, Allowed, false);
break;
case ARM::ARMV4T:
case ARM::ARMV5T:
case ARM::ARMV5TE:
case ARM::ARMV6:
case ARM::ARMV6J:
case ARM::AK_ARMV4T:
case ARM::AK_ARMV5T:
case ARM::AK_ARMV5TE:
case ARM::AK_ARMV6:
case ARM::AK_ARMV6J:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false);
break;
case ARM::ARMV6T2:
case ARM::AK_ARMV6T2:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break;
case ARM::ARMV6K:
case ARM::ARMV6Z:
case ARM::ARMV6ZK:
case ARM::AK_ARMV6K:
case ARM::AK_ARMV6Z:
case ARM::AK_ARMV6ZK:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(Virtualization_use, AllowTZ, false);
break;
case ARM::ARMV6M:
case ARM::AK_ARMV6M:
setAttributeItem(THUMB_ISA_use, Allowed, false);
break;
case ARM::ARMV7:
case ARM::AK_ARMV7:
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break;
case ARM::ARMV7A:
case ARM::AK_ARMV7A:
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break;
case ARM::ARMV7R:
case ARM::AK_ARMV7R:
setAttributeItem(CPU_arch_profile, RealTimeProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break;
case ARM::ARMV7M:
case ARM::AK_ARMV7M:
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break;
case ARM::ARMV8A:
case ARM::ARMV8_1A:
case ARM::AK_ARMV8A:
case ARM::AK_ARMV8_1A:
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
@ -767,13 +767,13 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
setAttributeItem(Virtualization_use, AllowTZVirtualization, false);
break;
case ARM::IWMMXT:
case ARM::AK_IWMMXT:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(WMMX_arch, AllowWMMXv1, false);
break;
case ARM::IWMMXT2:
case ARM::AK_IWMMXT2:
setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(WMMX_arch, AllowWMMXv2, false);
@ -789,38 +789,38 @@ void ARMTargetELFStreamer::emitFPU(unsigned Value) {
}
void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
switch (FPU) {
case ARM::VFP:
case ARM::VFPV2:
case ARM::FK_VFP:
case ARM::FK_VFPV2:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv2,
/* OverwriteExisting= */ false);
break;
case ARM::VFPV3:
case ARM::FK_VFPV3:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv3A,
/* OverwriteExisting= */ false);
break;
case ARM::VFPV3_D16:
case ARM::FK_VFPV3_D16:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv3B,
/* OverwriteExisting= */ false);
break;
case ARM::VFPV4:
case ARM::FK_VFPV4:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv4A,
/* OverwriteExisting= */ false);
break;
case ARM::VFPV4_D16:
case ARM::FK_VFPV4_D16:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv4B,
/* OverwriteExisting= */ false);
break;
case ARM::FP_ARMV8:
case ARM::FK_FP_ARMV8:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPARMv8A,
/* OverwriteExisting= */ false);
@ -828,13 +828,13 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
// FPV5_D16 is identical to FP_ARMV8 except for the number of D registers, so
// uses the FP_ARMV8_D16 build attribute.
case ARM::FPV5_D16:
case ARM::FK_FPV5_D16:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPARMv8B,
/* OverwriteExisting= */ false);
break;
case ARM::NEON:
case ARM::FK_NEON:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv3A,
/* OverwriteExisting= */ false);
@ -843,7 +843,7 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
/* OverwriteExisting= */ false);
break;
case ARM::NEON_VFPV4:
case ARM::FK_NEON_VFPV4:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPv4A,
/* OverwriteExisting= */ false);
@ -852,8 +852,8 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
/* OverwriteExisting= */ false);
break;
case ARM::NEON_FP_ARMV8:
case ARM::CRYPTO_NEON_FP_ARMV8:
case ARM::FK_NEON_FP_ARMV8:
case ARM::FK_CRYPTO_NEON_FP_ARMV8:
setAttributeItem(ARMBuildAttrs::FP_arch,
ARMBuildAttrs::AllowFPARMv8A,
/* OverwriteExisting= */ false);
@ -861,7 +861,7 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
// ARMAsmPrinter::emitAttributes(), depending on hasV8Ops() and hasV8_1a()
break;
case ARM::SOFTVFP:
case ARM::FK_SOFTVFP:
break;
default:
@ -902,10 +902,10 @@ void ARMTargetELFStreamer::finishAttributeSection() {
// ]+
// ]*
if (FPU != ARM::INVALID_FPU)
if (FPU != ARM::FK_INVALID)
emitFPUDefaultAttributes();
if (Arch != ARM::INVALID_ARCH)
if (Arch != ARM::AK_INVALID)
emitArchDefaultAttributes();
if (Contents.empty())
@ -965,7 +965,7 @@ void ARMTargetELFStreamer::finishAttributeSection() {
}
Contents.clear();
FPU = ARM::INVALID_FPU;
FPU = ARM::FK_INVALID;
}
void ARMTargetELFStreamer::emitLabel(MCSymbol *Symbol) {