mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
Change TargetParser enum names to avoid macro conflicts (llvm)
sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1" using a cpp macro. The result is that this fails to compile. Fixes https://llvm.org/PR23482 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237112 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -27,64 +27,64 @@ namespace llvm {
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namespace ARM {
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namespace ARM {
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// FPU names.
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// FPU names.
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enum FPUKind {
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enum FPUKind {
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INVALID_FPU = 0,
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FK_INVALID = 0,
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VFP,
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FK_VFP,
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VFPV2,
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FK_VFPV2,
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VFPV3,
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FK_VFPV3,
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VFPV3_D16,
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FK_VFPV3_D16,
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VFPV4,
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FK_VFPV4,
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VFPV4_D16,
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FK_VFPV4_D16,
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FPV5_D16,
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FK_FPV5_D16,
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FP_ARMV8,
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FK_FP_ARMV8,
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NEON,
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FK_NEON,
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NEON_VFPV4,
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FK_NEON_VFPV4,
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NEON_FP_ARMV8,
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FK_NEON_FP_ARMV8,
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CRYPTO_NEON_FP_ARMV8,
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FK_CRYPTO_NEON_FP_ARMV8,
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SOFTVFP,
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FK_SOFTVFP,
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LAST_FPU
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FK_LAST
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};
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};
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// Arch names.
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// Arch names.
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enum ArchKind {
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enum ArchKind {
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INVALID_ARCH = 0,
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AK_INVALID = 0,
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ARMV2,
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AK_ARMV2,
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ARMV2A,
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AK_ARMV2A,
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ARMV3,
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AK_ARMV3,
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ARMV3M,
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AK_ARMV3M,
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ARMV4,
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AK_ARMV4,
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ARMV4T,
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AK_ARMV4T,
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ARMV5,
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AK_ARMV5,
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ARMV5T,
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AK_ARMV5T,
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ARMV5TE,
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AK_ARMV5TE,
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ARMV6,
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AK_ARMV6,
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ARMV6J,
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AK_ARMV6J,
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ARMV6K,
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AK_ARMV6K,
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ARMV6T2,
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AK_ARMV6T2,
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ARMV6Z,
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AK_ARMV6Z,
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ARMV6ZK,
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AK_ARMV6ZK,
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ARMV6M,
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AK_ARMV6M,
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ARMV7,
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AK_ARMV7,
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ARMV7A,
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AK_ARMV7A,
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ARMV7R,
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AK_ARMV7R,
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ARMV7M,
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AK_ARMV7M,
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ARMV8A,
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AK_ARMV8A,
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ARMV8_1A,
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AK_ARMV8_1A,
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IWMMXT,
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AK_IWMMXT,
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IWMMXT2,
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AK_IWMMXT2,
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LAST_ARCH
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AK_LAST
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};
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};
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// Arch extension modifiers for CPUs.
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// Arch extension modifiers for CPUs.
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enum ArchExtKind {
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enum ArchExtKind {
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INVALID_ARCHEXT = 0,
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AEK_INVALID = 0,
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CRC,
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AEK_CRC,
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CRYPTO,
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AEK_CRYPTO,
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FP,
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AEK_FP,
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HWDIV,
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AEK_HWDIV,
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MP,
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AEK_MP,
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SEC,
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AEK_SEC,
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VIRT,
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AEK_VIRT,
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LAST_ARCHEXT
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AEK_LAST
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};
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};
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} // namespace ARM
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} // namespace ARM
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@ -27,20 +27,20 @@ struct {
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const char * Name;
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const char * Name;
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ARM::FPUKind ID;
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ARM::FPUKind ID;
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} FPUNames[] = {
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} FPUNames[] = {
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{ "invalid", ARM::INVALID_FPU },
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{ "invalid", ARM::FK_INVALID },
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{ "vfp", ARM::VFP },
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{ "vfp", ARM::FK_VFP },
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{ "vfpv2", ARM::VFPV2 },
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{ "vfpv2", ARM::FK_VFPV2 },
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{ "vfpv3", ARM::VFPV3 },
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{ "vfpv3", ARM::FK_VFPV3 },
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{ "vfpv3-d16", ARM::VFPV3_D16 },
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{ "vfpv3-d16", ARM::FK_VFPV3_D16 },
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{ "vfpv4", ARM::VFPV4 },
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{ "vfpv4", ARM::FK_VFPV4 },
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{ "vfpv4-d16", ARM::VFPV4_D16 },
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{ "vfpv4-d16", ARM::FK_VFPV4_D16 },
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{ "fpv5-d16", ARM::FPV5_D16 },
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{ "fpv5-d16", ARM::FK_FPV5_D16 },
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{ "fp-armv8", ARM::FP_ARMV8 },
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{ "fp-armv8", ARM::FK_FP_ARMV8 },
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{ "neon", ARM::NEON },
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{ "neon", ARM::FK_NEON },
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{ "neon-vfpv4", ARM::NEON_VFPV4 },
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{ "neon-vfpv4", ARM::FK_NEON_VFPV4 },
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{ "neon-fp-armv8", ARM::NEON_FP_ARMV8 },
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{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 },
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{ "crypto-neon-fp-armv8", ARM::CRYPTO_NEON_FP_ARMV8 },
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{ "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
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{ "softvfp", ARM::SOFTVFP }
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{ "softvfp", ARM::FK_SOFTVFP }
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};
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};
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// List of canonical arch names (use getArchSynonym)
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// List of canonical arch names (use getArchSynonym)
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// FIXME: TableGen this.
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// FIXME: TableGen this.
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@ -50,31 +50,31 @@ struct {
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const char *DefaultCPU;
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const char *DefaultCPU;
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ARMBuildAttrs::CPUArch DefaultArch;
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ARMBuildAttrs::CPUArch DefaultArch;
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} ARCHNames[] = {
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} ARCHNames[] = {
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{ "invalid", ARM::INVALID_ARCH, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2", ARM::ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2a", ARM::ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3", ARM::ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3m", ARM::ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4", ARM::ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4t", ARM::ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
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{ "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
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{ "armv5", ARM::ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5t", ARM::ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5te", ARM::ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6", ARM::ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6j", ARM::ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6k", ARM::ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
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{ "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
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{ "armv6t2", ARM::ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
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{ "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
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{ "armv6z", ARM::ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6zk", ARM::ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6-m", ARM::ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv7", ARM::ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-a", ARM::ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-r", ARM::ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-m", ARM::ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
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{ "armv8-a", ARM::ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8.1-a", ARM::ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
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{ "iwmmxt", ARM::IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
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{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
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{ "iwmmxt2", ARM::IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
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{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
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};
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};
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// List of canonical ARCH names (use getARCHSynonym)
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// List of canonical ARCH names (use getARCHSynonym)
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// FIXME: TableGen this.
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// FIXME: TableGen this.
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@ -82,14 +82,14 @@ struct {
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const char *Name;
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const char *Name;
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ARM::ArchExtKind ID;
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ARM::ArchExtKind ID;
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} ARCHExtNames[] = {
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} ARCHExtNames[] = {
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{ "invalid", ARM::INVALID_ARCHEXT },
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{ "invalid", ARM::AEK_INVALID },
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{ "crc", ARM::CRC },
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{ "crc", ARM::AEK_CRC },
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{ "crypto", ARM::CRYPTO },
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{ "crypto", ARM::AEK_CRYPTO },
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{ "fp", ARM::FP },
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{ "fp", ARM::AEK_FP },
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{ "idiv", ARM::HWDIV },
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{ "idiv", ARM::AEK_HWDIV },
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{ "mp", ARM::MP },
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{ "mp", ARM::AEK_MP },
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{ "sec", ARM::SEC },
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{ "sec", ARM::AEK_SEC },
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{ "virt", ARM::VIRT }
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{ "virt", ARM::AEK_VIRT }
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};
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};
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} // namespace
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} // namespace
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@ -101,31 +101,31 @@ namespace llvm {
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// ======================================================= //
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// ======================================================= //
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const char *ARMTargetParser::getFPUName(unsigned ID) {
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const char *ARMTargetParser::getFPUName(unsigned ID) {
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if (ID >= ARM::LAST_FPU)
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if (ID >= ARM::FK_LAST)
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return nullptr;
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return nullptr;
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return FPUNames[ID].Name;
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return FPUNames[ID].Name;
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}
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}
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const char *ARMTargetParser::getArchName(unsigned ID) {
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const char *ARMTargetParser::getArchName(unsigned ID) {
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if (ID >= ARM::LAST_ARCH)
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if (ID >= ARM::AK_LAST)
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return nullptr;
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return nullptr;
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return ARCHNames[ID].Name;
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return ARCHNames[ID].Name;
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}
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}
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const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) {
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const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) {
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if (ID >= ARM::LAST_ARCH)
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if (ID >= ARM::AK_LAST)
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return nullptr;
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return nullptr;
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return ARCHNames[ID].DefaultCPU;
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return ARCHNames[ID].DefaultCPU;
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}
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}
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unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) {
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unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) {
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if (ID >= ARM::LAST_ARCH)
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if (ID >= ARM::AK_LAST)
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return 0;
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return 0;
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return ARCHNames[ID].DefaultArch;
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return ARCHNames[ID].DefaultArch;
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}
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}
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const char *ARMTargetParser::getArchExtName(unsigned ID) {
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const char *ARMTargetParser::getArchExtName(unsigned ID) {
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if (ID >= ARM::LAST_ARCHEXT)
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if (ID >= ARM::AEK_LAST)
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return nullptr;
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return nullptr;
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return ARCHExtNames[ID].Name;
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return ARCHExtNames[ID].Name;
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}
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}
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@ -170,7 +170,7 @@ unsigned ARMTargetParser::parseFPU(StringRef FPU) {
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if (Syn == F.Name)
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if (Syn == F.Name)
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return F.ID;
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return F.ID;
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}
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}
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return ARM::INVALID_FPU;
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return ARM::FK_INVALID;
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}
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}
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unsigned ARMTargetParser::parseArch(StringRef Arch) {
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unsigned ARMTargetParser::parseArch(StringRef Arch) {
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@ -179,7 +179,7 @@ unsigned ARMTargetParser::parseArch(StringRef Arch) {
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if (Syn == A.Name)
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if (Syn == A.Name)
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return A.ID;
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return A.ID;
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}
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}
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return ARM::INVALID_ARCH;
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return ARM::AK_INVALID;
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}
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}
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unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
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unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
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@ -187,7 +187,7 @@ unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
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if (ArchExt == A.Name)
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if (ArchExt == A.Name)
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return A.ID;
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return A.ID;
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}
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}
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return ARM::INVALID_ARCHEXT;
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return ARM::AEK_INVALID;
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}
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}
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} // namespace llvm
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} // namespace llvm
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@ -591,7 +591,7 @@ void ARMAsmPrinter::emitAttributes() {
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// We consider krait as a "cortex-a9" + hwdiv CPU
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// We consider krait as a "cortex-a9" + hwdiv CPU
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// Enable hwdiv through ".arch_extension idiv"
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// Enable hwdiv through ".arch_extension idiv"
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if (STI.hasDivide() || STI.hasDivideInARMMode())
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if (STI.hasDivide() || STI.hasDivideInARMMode())
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ATS.emitArchExtension(ARM::HWDIV);
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ATS.emitArchExtension(ARM::AEK_HWDIV);
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} else
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} else
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ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
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ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
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}
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}
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@ -628,13 +628,13 @@ void ARMAsmPrinter::emitAttributes() {
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* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
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* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
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if (STI.hasFPARMv8()) {
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if (STI.hasFPARMv8()) {
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if (STI.hasCrypto())
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if (STI.hasCrypto())
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ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
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ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
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else
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else
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ATS.emitFPU(ARM::NEON_FP_ARMV8);
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ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
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} else if (STI.hasVFP4())
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} else if (STI.hasVFP4())
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ATS.emitFPU(ARM::NEON_VFPV4);
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ATS.emitFPU(ARM::FK_NEON_VFPV4);
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else
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else
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ATS.emitFPU(ARM::NEON);
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ATS.emitFPU(ARM::FK_NEON);
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// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
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// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
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if (STI.hasV8Ops())
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if (STI.hasV8Ops())
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ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
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ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
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@ -644,13 +644,13 @@ void ARMAsmPrinter::emitAttributes() {
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if (STI.hasFPARMv8())
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if (STI.hasFPARMv8())
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// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
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// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
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// FPU, but there are two different names for it depending on the CPU.
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// FPU, but there are two different names for it depending on the CPU.
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ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
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ATS.emitFPU(STI.hasD16() ? ARM::FK_FPV5_D16 : ARM::FK_FP_ARMV8);
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else if (STI.hasVFP4())
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else if (STI.hasVFP4())
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ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
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ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV4_D16 : ARM::FK_VFPV4);
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else if (STI.hasVFP3())
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else if (STI.hasVFP3())
|
||||||
ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
|
ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
|
||||||
else if (STI.hasVFP2())
|
else if (STI.hasVFP2())
|
||||||
ATS.emitFPU(ARM::VFPV2);
|
ATS.emitFPU(ARM::FK_VFPV2);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (TM.getRelocationModel() == Reloc::PIC_) {
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
||||||
|
@ -9041,7 +9041,7 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
|
|||||||
|
|
||||||
unsigned ID = ARMTargetParser::parseArch(Arch);
|
unsigned ID = ARMTargetParser::parseArch(Arch);
|
||||||
|
|
||||||
if (ID == ARM::INVALID_ARCH) {
|
if (ID == ARM::AK_INVALID) {
|
||||||
Error(L, "Unknown arch name");
|
Error(L, "Unknown arch name");
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -9190,49 +9190,49 @@ static const struct {
|
|||||||
const uint64_t Enabled;
|
const uint64_t Enabled;
|
||||||
const uint64_t Disabled;
|
const uint64_t Disabled;
|
||||||
} FPUs[] = {
|
} FPUs[] = {
|
||||||
{/* ID */ ARM::VFP,
|
{/* ID */ ARM::FK_VFP,
|
||||||
/* Enabled */ ARM::FeatureVFP2,
|
/* Enabled */ ARM::FeatureVFP2,
|
||||||
/* Disabled */ ARM::FeatureNEON},
|
/* Disabled */ ARM::FeatureNEON},
|
||||||
{/* ID */ ARM::VFPV2,
|
{/* ID */ ARM::FK_VFPV2,
|
||||||
/* Enabled */ ARM::FeatureVFP2,
|
/* Enabled */ ARM::FeatureVFP2,
|
||||||
/* Disabled */ ARM::FeatureNEON},
|
/* Disabled */ ARM::FeatureNEON},
|
||||||
{/* ID */ ARM::VFPV3,
|
{/* ID */ ARM::FK_VFPV3,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
|
||||||
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
|
||||||
{/* ID */ ARM::VFPV3_D16,
|
{/* ID */ ARM::FK_VFPV3_D16,
|
||||||
/* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
|
/* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
|
||||||
/* Disabled */ ARM::FeatureNEON},
|
/* Disabled */ ARM::FeatureNEON},
|
||||||
{/* ID */ ARM::VFPV4,
|
{/* ID */ ARM::FK_VFPV4,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
|
||||||
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
|
||||||
{/* ID */ ARM::VFPV4_D16,
|
{/* ID */ ARM::FK_VFPV4_D16,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureD16,
|
ARM::FeatureD16,
|
||||||
/* Disabled */ ARM::FeatureNEON},
|
/* Disabled */ ARM::FeatureNEON},
|
||||||
{/* ID */ ARM::FPV5_D16,
|
{/* ID */ ARM::FK_FPV5_D16,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureFPARMv8 | ARM::FeatureD16,
|
ARM::FeatureFPARMv8 | ARM::FeatureD16,
|
||||||
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
|
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
|
||||||
{/* ID */ ARM::FP_ARMV8,
|
{/* ID */ ARM::FK_FP_ARMV8,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureFPARMv8,
|
ARM::FeatureFPARMv8,
|
||||||
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
|
||||||
{/* ID */ ARM::NEON,
|
{/* ID */ ARM::FK_NEON,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
|
||||||
/* Disabled */ ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureD16},
|
||||||
{/* ID */ ARM::NEON_VFPV4,
|
{/* ID */ ARM::FK_NEON_VFPV4,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureNEON,
|
ARM::FeatureNEON,
|
||||||
/* Disabled */ ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureD16},
|
||||||
{/* ID */ ARM::NEON_FP_ARMV8,
|
{/* ID */ ARM::FK_NEON_FP_ARMV8,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureFPARMv8 | ARM::FeatureNEON,
|
ARM::FeatureFPARMv8 | ARM::FeatureNEON,
|
||||||
/* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
|
||||||
{/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
|
{/* ID */ ARM::FK_CRYPTO_NEON_FP_ARMV8,
|
||||||
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
/* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
|
||||||
ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
|
ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
|
||||||
/* Disabled */ ARM::FeatureD16},
|
/* Disabled */ ARM::FeatureD16},
|
||||||
{ARM::SOFTVFP, 0, 0},
|
{ARM::FK_SOFTVFP, 0, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
/// parseDirectiveFPU
|
/// parseDirectiveFPU
|
||||||
@ -9243,7 +9243,7 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
|
|||||||
|
|
||||||
unsigned ID = ARMTargetParser::parseFPU(FPU);
|
unsigned ID = ARMTargetParser::parseFPU(FPU);
|
||||||
|
|
||||||
if (ID == ARM::INVALID_FPU) {
|
if (ID == ARM::FK_INVALID) {
|
||||||
Error(FPUNameLoc, "Unknown FPU name");
|
Error(FPUNameLoc, "Unknown FPU name");
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
@ -9897,7 +9897,7 @@ bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
|
|||||||
|
|
||||||
unsigned ID = ARMTargetParser::parseArch(Arch);
|
unsigned ID = ARMTargetParser::parseArch(Arch);
|
||||||
|
|
||||||
if (ID == ARM::INVALID_ARCH) {
|
if (ID == ARM::AK_INVALID) {
|
||||||
Error(ArchLoc, "unknown architecture '" + Arch + "'");
|
Error(ArchLoc, "unknown architecture '" + Arch + "'");
|
||||||
Parser.eatToEndOfStatement();
|
Parser.eatToEndOfStatement();
|
||||||
return false;
|
return false;
|
||||||
|
@ -386,8 +386,8 @@ private:
|
|||||||
|
|
||||||
public:
|
public:
|
||||||
ARMTargetELFStreamer(MCStreamer &S)
|
ARMTargetELFStreamer(MCStreamer &S)
|
||||||
: ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::INVALID_FPU),
|
: ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID),
|
||||||
Arch(ARM::INVALID_ARCH), EmittedArch(ARM::INVALID_ARCH),
|
Arch(ARM::AK_INVALID), EmittedArch(ARM::AK_INVALID),
|
||||||
AttributeSection(nullptr) {}
|
AttributeSection(nullptr) {}
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -692,7 +692,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
|
|||||||
ARMTargetParser::getArchDefaultCPUName(Arch),
|
ARMTargetParser::getArchDefaultCPUName(Arch),
|
||||||
false);
|
false);
|
||||||
|
|
||||||
if (EmittedArch == ARM::INVALID_ARCH)
|
if (EmittedArch == ARM::AK_INVALID)
|
||||||
setAttributeItem(CPU_arch,
|
setAttributeItem(CPU_arch,
|
||||||
ARMTargetParser::getArchDefaultCPUArch(Arch),
|
ARMTargetParser::getArchDefaultCPUArch(Arch),
|
||||||
false);
|
false);
|
||||||
@ -702,64 +702,64 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
|
|||||||
false);
|
false);
|
||||||
|
|
||||||
switch (Arch) {
|
switch (Arch) {
|
||||||
case ARM::ARMV2:
|
case ARM::AK_ARMV2:
|
||||||
case ARM::ARMV2A:
|
case ARM::AK_ARMV2A:
|
||||||
case ARM::ARMV3:
|
case ARM::AK_ARMV3:
|
||||||
case ARM::ARMV3M:
|
case ARM::AK_ARMV3M:
|
||||||
case ARM::ARMV4:
|
case ARM::AK_ARMV4:
|
||||||
case ARM::ARMV5:
|
case ARM::AK_ARMV5:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV4T:
|
case ARM::AK_ARMV4T:
|
||||||
case ARM::ARMV5T:
|
case ARM::AK_ARMV5T:
|
||||||
case ARM::ARMV5TE:
|
case ARM::AK_ARMV5TE:
|
||||||
case ARM::ARMV6:
|
case ARM::AK_ARMV6:
|
||||||
case ARM::ARMV6J:
|
case ARM::AK_ARMV6J:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV6T2:
|
case ARM::AK_ARMV6T2:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV6K:
|
case ARM::AK_ARMV6K:
|
||||||
case ARM::ARMV6Z:
|
case ARM::AK_ARMV6Z:
|
||||||
case ARM::ARMV6ZK:
|
case ARM::AK_ARMV6ZK:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
||||||
setAttributeItem(Virtualization_use, AllowTZ, false);
|
setAttributeItem(Virtualization_use, AllowTZ, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV6M:
|
case ARM::AK_ARMV6M:
|
||||||
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV7:
|
case ARM::AK_ARMV7:
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV7A:
|
case ARM::AK_ARMV7A:
|
||||||
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV7R:
|
case ARM::AK_ARMV7R:
|
||||||
setAttributeItem(CPU_arch_profile, RealTimeProfile, false);
|
setAttributeItem(CPU_arch_profile, RealTimeProfile, false);
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV7M:
|
case ARM::AK_ARMV7M:
|
||||||
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
|
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::ARMV8A:
|
case ARM::AK_ARMV8A:
|
||||||
case ARM::ARMV8_1A:
|
case ARM::AK_ARMV8_1A:
|
||||||
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
||||||
@ -767,13 +767,13 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
|
|||||||
setAttributeItem(Virtualization_use, AllowTZVirtualization, false);
|
setAttributeItem(Virtualization_use, AllowTZVirtualization, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::IWMMXT:
|
case ARM::AK_IWMMXT:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
||||||
setAttributeItem(WMMX_arch, AllowWMMXv1, false);
|
setAttributeItem(WMMX_arch, AllowWMMXv1, false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::IWMMXT2:
|
case ARM::AK_IWMMXT2:
|
||||||
setAttributeItem(ARM_ISA_use, Allowed, false);
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
||||||
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
||||||
setAttributeItem(WMMX_arch, AllowWMMXv2, false);
|
setAttributeItem(WMMX_arch, AllowWMMXv2, false);
|
||||||
@ -789,38 +789,38 @@ void ARMTargetELFStreamer::emitFPU(unsigned Value) {
|
|||||||
}
|
}
|
||||||
void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
||||||
switch (FPU) {
|
switch (FPU) {
|
||||||
case ARM::VFP:
|
case ARM::FK_VFP:
|
||||||
case ARM::VFPV2:
|
case ARM::FK_VFPV2:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv2,
|
ARMBuildAttrs::AllowFPv2,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::VFPV3:
|
case ARM::FK_VFPV3:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv3A,
|
ARMBuildAttrs::AllowFPv3A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::VFPV3_D16:
|
case ARM::FK_VFPV3_D16:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv3B,
|
ARMBuildAttrs::AllowFPv3B,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::VFPV4:
|
case ARM::FK_VFPV4:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv4A,
|
ARMBuildAttrs::AllowFPv4A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::VFPV4_D16:
|
case ARM::FK_VFPV4_D16:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv4B,
|
ARMBuildAttrs::AllowFPv4B,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::FP_ARMV8:
|
case ARM::FK_FP_ARMV8:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPARMv8A,
|
ARMBuildAttrs::AllowFPARMv8A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
@ -828,13 +828,13 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
|||||||
|
|
||||||
// FPV5_D16 is identical to FP_ARMV8 except for the number of D registers, so
|
// FPV5_D16 is identical to FP_ARMV8 except for the number of D registers, so
|
||||||
// uses the FP_ARMV8_D16 build attribute.
|
// uses the FP_ARMV8_D16 build attribute.
|
||||||
case ARM::FPV5_D16:
|
case ARM::FK_FPV5_D16:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPARMv8B,
|
ARMBuildAttrs::AllowFPARMv8B,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::NEON:
|
case ARM::FK_NEON:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv3A,
|
ARMBuildAttrs::AllowFPv3A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
@ -843,7 +843,7 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
|||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::NEON_VFPV4:
|
case ARM::FK_NEON_VFPV4:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPv4A,
|
ARMBuildAttrs::AllowFPv4A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
@ -852,8 +852,8 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
|||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::NEON_FP_ARMV8:
|
case ARM::FK_NEON_FP_ARMV8:
|
||||||
case ARM::CRYPTO_NEON_FP_ARMV8:
|
case ARM::FK_CRYPTO_NEON_FP_ARMV8:
|
||||||
setAttributeItem(ARMBuildAttrs::FP_arch,
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
||||||
ARMBuildAttrs::AllowFPARMv8A,
|
ARMBuildAttrs::AllowFPARMv8A,
|
||||||
/* OverwriteExisting= */ false);
|
/* OverwriteExisting= */ false);
|
||||||
@ -861,7 +861,7 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
|||||||
// ARMAsmPrinter::emitAttributes(), depending on hasV8Ops() and hasV8_1a()
|
// ARMAsmPrinter::emitAttributes(), depending on hasV8Ops() and hasV8_1a()
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ARM::SOFTVFP:
|
case ARM::FK_SOFTVFP:
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
@ -902,10 +902,10 @@ void ARMTargetELFStreamer::finishAttributeSection() {
|
|||||||
// ]+
|
// ]+
|
||||||
// ]*
|
// ]*
|
||||||
|
|
||||||
if (FPU != ARM::INVALID_FPU)
|
if (FPU != ARM::FK_INVALID)
|
||||||
emitFPUDefaultAttributes();
|
emitFPUDefaultAttributes();
|
||||||
|
|
||||||
if (Arch != ARM::INVALID_ARCH)
|
if (Arch != ARM::AK_INVALID)
|
||||||
emitArchDefaultAttributes();
|
emitArchDefaultAttributes();
|
||||||
|
|
||||||
if (Contents.empty())
|
if (Contents.empty())
|
||||||
@ -965,7 +965,7 @@ void ARMTargetELFStreamer::finishAttributeSection() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
Contents.clear();
|
Contents.clear();
|
||||||
FPU = ARM::INVALID_FPU;
|
FPU = ARM::FK_INVALID;
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARMTargetELFStreamer::emitLabel(MCSymbol *Symbol) {
|
void ARMTargetELFStreamer::emitLabel(MCSymbol *Symbol) {
|
||||||
|
Loading…
Reference in New Issue
Block a user