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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-17 20:23:59 +00:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -3347,7 +3347,7 @@ public:
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InstructionShuffler(bool alternate, bool topdown)
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InstructionShuffler(bool alternate, bool topdown)
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: IsAlternating(alternate), IsTopDown(topdown) {}
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: IsAlternating(alternate), IsTopDown(topdown) {}
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virtual void initialize(ScheduleDAGMI*) {
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void initialize(ScheduleDAGMI*) override {
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TopQ.clear();
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TopQ.clear();
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BottomQ.clear();
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BottomQ.clear();
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}
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}
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@ -3355,7 +3355,7 @@ public:
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/// Implement MachineSchedStrategy interface.
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/// Implement MachineSchedStrategy interface.
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/// -----------------------------------------
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/// -----------------------------------------
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virtual SUnit *pickNode(bool &IsTopNode) {
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SUnit *pickNode(bool &IsTopNode) override {
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SUnit *SU;
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SUnit *SU;
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if (IsTopDown) {
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if (IsTopDown) {
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do {
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do {
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@ -3378,12 +3378,12 @@ public:
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return SU;
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return SU;
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}
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}
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virtual void schedNode(SUnit *SU, bool IsTopNode) {}
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void schedNode(SUnit *SU, bool IsTopNode) override {}
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virtual void releaseTopNode(SUnit *SU) {
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void releaseTopNode(SUnit *SU) override {
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TopQ.push(SU);
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TopQ.push(SU);
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}
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}
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virtual void releaseBottomNode(SUnit *SU) {
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void releaseBottomNode(SUnit *SU) override {
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BottomQ.push(SU);
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BottomQ.push(SU);
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}
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}
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};
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};
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@ -1784,7 +1784,7 @@ public:
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}
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void dump(ScheduleDAG *DAG) const {
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void dump(ScheduleDAG *DAG) const override {
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// Emulate pop() without clobbering NodeQueueIds.
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// Emulate pop() without clobbering NodeQueueIds.
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std::vector<SUnit*> DumpQueue = Queue;
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std::vector<SUnit*> DumpQueue = Queue;
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SF DumpPicker = Picker;
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SF DumpPicker = Picker;
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@ -52,7 +52,7 @@ class InstrProfErrorCategoryType : public error_category {
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}
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}
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llvm_unreachable("A value of instrprof_error has no message.");
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llvm_unreachable("A value of instrprof_error has no message.");
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}
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}
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error_condition default_error_condition(int EV) const {
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error_condition default_error_condition(int EV) const override {
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if (EV == instrprof_error::success)
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if (EV == instrprof_error::success)
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return errc::success;
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return errc::success;
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return errc::invalid_argument;
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return errc::invalid_argument;
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@ -57,7 +57,7 @@ public:
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const override;
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RegScavenger *RS) const override;
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void adjustForSegmentedStacks(MachineFunction &MF) const;
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void adjustForSegmentedStacks(MachineFunction &MF) const override;
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private:
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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@ -25,9 +25,9 @@ public:
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static char ID;
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static char ID;
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ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
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ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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bool runOnMachineFunction(MachineFunction &Fn) override;
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virtual const char *getPassName() const {
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const char *getPassName() const override {
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return "optimise barriers pass";
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return "optimise barriers pass";
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}
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}
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@ -101,7 +101,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
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/// ARMLETargetMachine - ARM little endian target machine.
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/// ARMLETargetMachine - ARM little endian target machine.
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///
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///
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class ARMLETargetMachine : public ARMTargetMachine {
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class ARMLETargetMachine : public ARMTargetMachine {
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virtual void anchor();
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void anchor() override;
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public:
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public:
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ARMLETargetMachine(const Target &T, StringRef TT,
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ARMLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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@ -112,7 +112,7 @@ public:
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/// ARMBETargetMachine - ARM big endian target machine.
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/// ARMBETargetMachine - ARM big endian target machine.
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///
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///
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class ARMBETargetMachine : public ARMTargetMachine {
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class ARMBETargetMachine : public ARMTargetMachine {
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virtual void anchor();
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void anchor() override;
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public:
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public:
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ARMBETargetMachine(const Target &T, StringRef TT,
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ARMBETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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@ -168,7 +168,7 @@ public:
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/// ThumbLETargetMachine - Thumb little endian target machine.
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/// ThumbLETargetMachine - Thumb little endian target machine.
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///
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///
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class ThumbLETargetMachine : public ThumbTargetMachine {
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class ThumbLETargetMachine : public ThumbTargetMachine {
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virtual void anchor();
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void anchor() override;
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public:
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public:
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ThumbLETargetMachine(const Target &T, StringRef TT,
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ThumbLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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@ -179,7 +179,7 @@ public:
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/// ThumbBETargetMachine - Thumb big endian target machine.
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/// ThumbBETargetMachine - Thumb big endian target machine.
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///
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///
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class ThumbBETargetMachine : public ThumbTargetMachine {
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class ThumbBETargetMachine : public ThumbTargetMachine {
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virtual void anchor();
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void anchor() override;
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public:
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public:
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ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
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ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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StringRef FS, const TargetOptions &Options,
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@ -35,13 +35,13 @@ namespace llvm {
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};
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};
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class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
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class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
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void anchor();
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void anchor() override;
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public:
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public:
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explicit ARMCOFFMCAsmInfoMicrosoft();
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explicit ARMCOFFMCAsmInfoMicrosoft();
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};
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};
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class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF {
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class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF {
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void anchor();
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void anchor() override;
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public:
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public:
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explicit ARMCOFFMCAsmInfoGNU();
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explicit ARMCOFFMCAsmInfoGNU();
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};
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};
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@ -108,9 +108,9 @@ namespace {
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explicit CppWriter(formatted_raw_ostream &o) :
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explicit CppWriter(formatted_raw_ostream &o) :
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ModulePass(ID), Out(o), uniqueNum(0), is_inline(false), indent_level(0){}
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ModulePass(ID), Out(o), uniqueNum(0), is_inline(false), indent_level(0){}
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virtual const char *getPassName() const { return "C++ backend"; }
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const char *getPassName() const override { return "C++ backend"; }
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bool runOnModule(Module &M);
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bool runOnModule(Module &M) override;
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void printProgram(const std::string& fname, const std::string& modName );
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void printProgram(const std::string& fname, const std::string& modName );
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void printModule(const std::string& fname, const std::string& modName );
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void printModule(const std::string& fname, const std::string& modName );
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@ -28,14 +28,12 @@ struct CPPTargetMachine : public TargetMachine {
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CodeGenOpt::Level OL)
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CodeGenOpt::Level OL)
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: TargetMachine(T, TT, CPU, FS, Options) {}
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: TargetMachine(T, TT, CPU, FS, Options) {}
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virtual bool addPassesToEmitFile(PassManagerBase &PM,
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bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
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formatted_raw_ostream &Out,
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CodeGenFileType FileType, bool DisableVerify,
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CodeGenFileType FileType,
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bool DisableVerify,
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AnalysisID StartAfter,
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AnalysisID StartAfter,
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AnalysisID StopAfter);
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AnalysisID StopAfter) override;
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virtual const DataLayout *getDataLayout() const { return nullptr; }
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const DataLayout *getDataLayout() const override { return nullptr; }
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};
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};
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extern Target TheCppBackendTarget;
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extern Target TheCppBackendTarget;
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@ -71,7 +71,7 @@ public:
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}
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}
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bool processBlock(MachineBasicBlock &MBB);
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F) override;
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private:
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private:
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Reference getRegReferences(MachineInstr *MI, unsigned Reg);
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Reference getRegReferences(MachineInstr *MI, unsigned Reg);
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@ -138,7 +138,7 @@ public:
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return "SystemZ Long Branch";
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return "SystemZ Long Branch";
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}
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}
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F) override;
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private:
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private:
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void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
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void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
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@ -31,7 +31,7 @@ public:
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}
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}
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bool processBlock(MachineBasicBlock &MBB);
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F);
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bool runOnMachineFunction(MachineFunction &F) override;
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private:
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private:
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bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
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bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
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@ -782,7 +782,7 @@ namespace llvm {
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Type *Ty) const override;
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Type *Ty) const override;
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/// Intel processors have a unified instruction and data cache
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/// Intel processors have a unified instruction and data cache
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const char * getClearCacheBuiltinName() const {
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const char * getClearCacheBuiltinName() const override {
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return nullptr; // nothing to do, move along.
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return nullptr; // nothing to do, move along.
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}
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}
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