[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2014-04-29 07:58:41 +00:00
parent 0fd57f4b56
commit eda7f44b27
13 changed files with 27 additions and 29 deletions

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@ -3347,7 +3347,7 @@ public:
InstructionShuffler(bool alternate, bool topdown) InstructionShuffler(bool alternate, bool topdown)
: IsAlternating(alternate), IsTopDown(topdown) {} : IsAlternating(alternate), IsTopDown(topdown) {}
virtual void initialize(ScheduleDAGMI*) { void initialize(ScheduleDAGMI*) override {
TopQ.clear(); TopQ.clear();
BottomQ.clear(); BottomQ.clear();
} }
@ -3355,7 +3355,7 @@ public:
/// Implement MachineSchedStrategy interface. /// Implement MachineSchedStrategy interface.
/// ----------------------------------------- /// -----------------------------------------
virtual SUnit *pickNode(bool &IsTopNode) { SUnit *pickNode(bool &IsTopNode) override {
SUnit *SU; SUnit *SU;
if (IsTopDown) { if (IsTopDown) {
do { do {
@ -3378,12 +3378,12 @@ public:
return SU; return SU;
} }
virtual void schedNode(SUnit *SU, bool IsTopNode) {} void schedNode(SUnit *SU, bool IsTopNode) override {}
virtual void releaseTopNode(SUnit *SU) { void releaseTopNode(SUnit *SU) override {
TopQ.push(SU); TopQ.push(SU);
} }
virtual void releaseBottomNode(SUnit *SU) { void releaseBottomNode(SUnit *SU) override {
BottomQ.push(SU); BottomQ.push(SU);
} }
}; };

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@ -1784,7 +1784,7 @@ public:
} }
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dump(ScheduleDAG *DAG) const { void dump(ScheduleDAG *DAG) const override {
// Emulate pop() without clobbering NodeQueueIds. // Emulate pop() without clobbering NodeQueueIds.
std::vector<SUnit*> DumpQueue = Queue; std::vector<SUnit*> DumpQueue = Queue;
SF DumpPicker = Picker; SF DumpPicker = Picker;

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@ -52,7 +52,7 @@ class InstrProfErrorCategoryType : public error_category {
} }
llvm_unreachable("A value of instrprof_error has no message."); llvm_unreachable("A value of instrprof_error has no message.");
} }
error_condition default_error_condition(int EV) const { error_condition default_error_condition(int EV) const override {
if (EV == instrprof_error::success) if (EV == instrprof_error::success)
return errc::success; return errc::success;
return errc::invalid_argument; return errc::invalid_argument;

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@ -57,7 +57,7 @@ public:
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const override; RegScavenger *RS) const override;
void adjustForSegmentedStacks(MachineFunction &MF) const; void adjustForSegmentedStacks(MachineFunction &MF) const override;
private: private:
void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,

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@ -25,9 +25,9 @@ public:
static char ID; static char ID;
ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {} ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "optimise barriers pass"; return "optimise barriers pass";
} }

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@ -101,7 +101,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
/// ARMLETargetMachine - ARM little endian target machine. /// ARMLETargetMachine - ARM little endian target machine.
/// ///
class ARMLETargetMachine : public ARMTargetMachine { class ARMLETargetMachine : public ARMTargetMachine {
virtual void anchor(); void anchor() override;
public: public:
ARMLETargetMachine(const Target &T, StringRef TT, ARMLETargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS, const TargetOptions &Options,
@ -112,7 +112,7 @@ public:
/// ARMBETargetMachine - ARM big endian target machine. /// ARMBETargetMachine - ARM big endian target machine.
/// ///
class ARMBETargetMachine : public ARMTargetMachine { class ARMBETargetMachine : public ARMTargetMachine {
virtual void anchor(); void anchor() override;
public: public:
ARMBETargetMachine(const Target &T, StringRef TT, ARMBETargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS, const TargetOptions &Options,
@ -168,7 +168,7 @@ public:
/// ThumbLETargetMachine - Thumb little endian target machine. /// ThumbLETargetMachine - Thumb little endian target machine.
/// ///
class ThumbLETargetMachine : public ThumbTargetMachine { class ThumbLETargetMachine : public ThumbTargetMachine {
virtual void anchor(); void anchor() override;
public: public:
ThumbLETargetMachine(const Target &T, StringRef TT, ThumbLETargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS, const TargetOptions &Options,
@ -179,7 +179,7 @@ public:
/// ThumbBETargetMachine - Thumb big endian target machine. /// ThumbBETargetMachine - Thumb big endian target machine.
/// ///
class ThumbBETargetMachine : public ThumbTargetMachine { class ThumbBETargetMachine : public ThumbTargetMachine {
virtual void anchor(); void anchor() override;
public: public:
ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,

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@ -35,13 +35,13 @@ namespace llvm {
}; };
class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { class ARMCOFFMCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
void anchor(); void anchor() override;
public: public:
explicit ARMCOFFMCAsmInfoMicrosoft(); explicit ARMCOFFMCAsmInfoMicrosoft();
}; };
class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF { class ARMCOFFMCAsmInfoGNU : public MCAsmInfoGNUCOFF {
void anchor(); void anchor() override;
public: public:
explicit ARMCOFFMCAsmInfoGNU(); explicit ARMCOFFMCAsmInfoGNU();
}; };

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@ -108,9 +108,9 @@ namespace {
explicit CppWriter(formatted_raw_ostream &o) : explicit CppWriter(formatted_raw_ostream &o) :
ModulePass(ID), Out(o), uniqueNum(0), is_inline(false), indent_level(0){} ModulePass(ID), Out(o), uniqueNum(0), is_inline(false), indent_level(0){}
virtual const char *getPassName() const { return "C++ backend"; } const char *getPassName() const override { return "C++ backend"; }
bool runOnModule(Module &M); bool runOnModule(Module &M) override;
void printProgram(const std::string& fname, const std::string& modName ); void printProgram(const std::string& fname, const std::string& modName );
void printModule(const std::string& fname, const std::string& modName ); void printModule(const std::string& fname, const std::string& modName );

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@ -28,14 +28,12 @@ struct CPPTargetMachine : public TargetMachine {
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS, Options) {} : TargetMachine(T, TT, CPU, FS, Options) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM, bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
formatted_raw_ostream &Out, CodeGenFileType FileType, bool DisableVerify,
CodeGenFileType FileType,
bool DisableVerify,
AnalysisID StartAfter, AnalysisID StartAfter,
AnalysisID StopAfter); AnalysisID StopAfter) override;
virtual const DataLayout *getDataLayout() const { return nullptr; } const DataLayout *getDataLayout() const override { return nullptr; }
}; };
extern Target TheCppBackendTarget; extern Target TheCppBackendTarget;

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@ -71,7 +71,7 @@ public:
} }
bool processBlock(MachineBasicBlock &MBB); bool processBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
private: private:
Reference getRegReferences(MachineInstr *MI, unsigned Reg); Reference getRegReferences(MachineInstr *MI, unsigned Reg);

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@ -138,7 +138,7 @@ public:
return "SystemZ Long Branch"; return "SystemZ Long Branch";
} }
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
private: private:
void skipNonTerminators(BlockPosition &Position, MBBInfo &Block); void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);

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@ -31,7 +31,7 @@ public:
} }
bool processBlock(MachineBasicBlock &MBB); bool processBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
private: private:
bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther, bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,

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@ -782,7 +782,7 @@ namespace llvm {
Type *Ty) const override; Type *Ty) const override;
/// Intel processors have a unified instruction and data cache /// Intel processors have a unified instruction and data cache
const char * getClearCacheBuiltinName() const { const char * getClearCacheBuiltinName() const override {
return nullptr; // nothing to do, move along. return nullptr; // nothing to do, move along.
} }