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https://github.com/c64scene-ar/llvm-6502.git
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Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -71,6 +71,9 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ", " << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -87,10 +90,14 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << '\t' << getRegisterName(Dst.getReg())
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<< ", " << getRegisterName(MO1.getReg());
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if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
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if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -104,6 +111,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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@@ -111,6 +119,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << '\t' << "push";
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printPredicateOperand(MI, 4, O);
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O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -123,6 +132,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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@@ -130,6 +140,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << '\t' << "pop";
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printPredicateOperand(MI, 5, O);
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O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -141,6 +152,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -151,6 +163,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -169,6 +182,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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if (Writeback) O << "!";
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O << ", ";
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printRegisterList(MI, 3, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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@@ -177,10 +191,12 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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MI->getOperand(1).getReg() == ARM::R8) {
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O << "\tnop";
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printPredicateOperand(MI, 2, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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return;
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}
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printInstruction(MI, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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