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Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-20 23:34:39 +00:00
parent 7bc3178182
commit ee04a6d3a4
29 changed files with 200 additions and 192 deletions
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2
lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -8,8 +8,8 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMFixupKinds.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCDirectives.h"

4
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -15,15 +15,15 @@
#define DEBUG_TYPE "asm-printer"
#include "ARM.h"
#include "ARMAsmPrinter.h"
#include "ARMAddressingModes.h"
#include "ARMBuildAttrs.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMMCExpr.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "InstPrinter/ARMInstPrinter.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Constants.h"
#include "llvm/Module.h"

139
lib/Target/ARM/ARMBaseInfo.h
View File

@ -191,6 +191,9 @@ inline static unsigned getARMRegisterNumbering(unsigned Reg) {
}
}
/// ARMII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace ARMII {
/// ARM Index Modes
@ -287,6 +290,142 @@ namespace ARMII {
/// call operand.
MO_PLT
};
enum {
//===------------------------------------------------------------------===//
// Instruction Flags.
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
// The index mode enums are declared in ARMBaseInfo.h
IndexModeShift = 5,
IndexModeMask = 3 << IndexModeShift,
//===------------------------------------------------------------------===//
// Instruction encoding formats.
//
FormShift = 7,
FormMask = 0x3f << FormShift,
// Pseudo instructions
Pseudo = 0 << FormShift,
// Multiply instructions
MulFrm = 1 << FormShift,
// Branch instructions
BrFrm = 2 << FormShift,
BrMiscFrm = 3 << FormShift,
// Data Processing instructions
DPFrm = 4 << FormShift,
DPSoRegFrm = 5 << FormShift,
// Load and Store
LdFrm = 6 << FormShift,
StFrm = 7 << FormShift,
LdMiscFrm = 8 << FormShift,
StMiscFrm = 9 << FormShift,
LdStMulFrm = 10 << FormShift,
LdStExFrm = 11 << FormShift,
// Miscellaneous arithmetic instructions
ArithMiscFrm = 12 << FormShift,
SatFrm = 13 << FormShift,
// Extend instructions
ExtFrm = 14 << FormShift,
// VFP formats
VFPUnaryFrm = 15 << FormShift,
VFPBinaryFrm = 16 << FormShift,
VFPConv1Frm = 17 << FormShift,
VFPConv2Frm = 18 << FormShift,
VFPConv3Frm = 19 << FormShift,
VFPConv4Frm = 20 << FormShift,
VFPConv5Frm = 21 << FormShift,
VFPLdStFrm = 22 << FormShift,
VFPLdStMulFrm = 23 << FormShift,
VFPMiscFrm = 24 << FormShift,
// Thumb format
ThumbFrm = 25 << FormShift,
// Miscelleaneous format
MiscFrm = 26 << FormShift,
// NEON formats
NGetLnFrm = 27 << FormShift,
NSetLnFrm = 28 << FormShift,
NDupFrm = 29 << FormShift,
NLdStFrm = 30 << FormShift,
N1RegModImmFrm= 31 << FormShift,
N2RegFrm = 32 << FormShift,
NVCVTFrm = 33 << FormShift,
NVDupLnFrm = 34 << FormShift,
N2RegVShLFrm = 35 << FormShift,
N2RegVShRFrm = 36 << FormShift,
N3RegFrm = 37 << FormShift,
N3RegVShFrm = 38 << FormShift,
NVExtFrm = 39 << FormShift,
NVMulSLFrm = 40 << FormShift,
NVTBLFrm = 41 << FormShift,
//===------------------------------------------------------------------===//
// Misc flags.
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
UnaryDP = 1 << 13,
// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
// a 16-bit Thumb instruction if certain conditions are met.
Xform16Bit = 1 << 14,
//===------------------------------------------------------------------===//
// Code domain.
DomainShift = 15,
DomainMask = 7 << DomainShift,
DomainGeneral = 0 << DomainShift,
DomainVFP = 1 << DomainShift,
DomainNEON = 2 << DomainShift,
DomainNEONA8 = 4 << DomainShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
// machine instructions.
//
// FIXME: This list will need adjusting/fixing as the MC code emitter
// takes shape and the ARMCodeEmitter.cpp bits go away.
ShiftTypeShift = 4,
M_BitShift = 5,
ShiftImmShift = 5,
ShiftShift = 7,
N_BitShift = 7,
ImmHiShift = 8,
SoRotImmShift = 8,
RegRsShift = 8,
ExtRotImmShift = 10,
RegRdLoShift = 12,
RegRdShift = 12,
RegRdHiShift = 16,
RegRnShift = 16,
S_BitShift = 20,
W_BitShift = 21,
AM3_I_BitShift = 22,
D_BitShift = 22,
U_BitShift = 23,
P_BitShift = 24,
I_BitShift = 25,
CondShift = 28
};
} // end namespace ARMII
} // end namespace llvm;

3
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -13,11 +13,11 @@
#include "ARMBaseInstrInfo.h"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMConstantPoolValue.h"
#include "ARMHazardRecognizer.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/GlobalValue.h"
@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"

140
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -27,146 +27,6 @@ namespace llvm {
class ARMSubtarget;
class ARMBaseRegisterInfo;
/// ARMII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace ARMII {
enum {
//===------------------------------------------------------------------===//
// Instruction Flags.
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
// The index mode enums are declared in ARMBaseInfo.h
IndexModeShift = 5,
IndexModeMask = 3 << IndexModeShift,
//===------------------------------------------------------------------===//
// Instruction encoding formats.
//
FormShift = 7,
FormMask = 0x3f << FormShift,
// Pseudo instructions
Pseudo = 0 << FormShift,
// Multiply instructions
MulFrm = 1 << FormShift,
// Branch instructions
BrFrm = 2 << FormShift,
BrMiscFrm = 3 << FormShift,
// Data Processing instructions
DPFrm = 4 << FormShift,
DPSoRegFrm = 5 << FormShift,
// Load and Store
LdFrm = 6 << FormShift,
StFrm = 7 << FormShift,
LdMiscFrm = 8 << FormShift,
StMiscFrm = 9 << FormShift,
LdStMulFrm = 10 << FormShift,
LdStExFrm = 11 << FormShift,
// Miscellaneous arithmetic instructions
ArithMiscFrm = 12 << FormShift,
SatFrm = 13 << FormShift,
// Extend instructions
ExtFrm = 14 << FormShift,
// VFP formats
VFPUnaryFrm = 15 << FormShift,
VFPBinaryFrm = 16 << FormShift,
VFPConv1Frm = 17 << FormShift,
VFPConv2Frm = 18 << FormShift,
VFPConv3Frm = 19 << FormShift,
VFPConv4Frm = 20 << FormShift,
VFPConv5Frm = 21 << FormShift,
VFPLdStFrm = 22 << FormShift,
VFPLdStMulFrm = 23 << FormShift,
VFPMiscFrm = 24 << FormShift,
// Thumb format
ThumbFrm = 25 << FormShift,
// Miscelleaneous format
MiscFrm = 26 << FormShift,
// NEON formats
NGetLnFrm = 27 << FormShift,
NSetLnFrm = 28 << FormShift,
NDupFrm = 29 << FormShift,
NLdStFrm = 30 << FormShift,
N1RegModImmFrm= 31 << FormShift,
N2RegFrm = 32 << FormShift,
NVCVTFrm = 33 << FormShift,
NVDupLnFrm = 34 << FormShift,
N2RegVShLFrm = 35 << FormShift,
N2RegVShRFrm = 36 << FormShift,
N3RegFrm = 37 << FormShift,
N3RegVShFrm = 38 << FormShift,
NVExtFrm = 39 << FormShift,
NVMulSLFrm = 40 << FormShift,
NVTBLFrm = 41 << FormShift,
//===------------------------------------------------------------------===//
// Misc flags.
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
UnaryDP = 1 << 13,
// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
// a 16-bit Thumb instruction if certain conditions are met.
Xform16Bit = 1 << 14,
//===------------------------------------------------------------------===//
// Code domain.
DomainShift = 15,
DomainMask = 7 << DomainShift,
DomainGeneral = 0 << DomainShift,
DomainVFP = 1 << DomainShift,
DomainNEON = 2 << DomainShift,
DomainNEONA8 = 4 << DomainShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
// machine instructions.
//
// FIXME: This list will need adjusting/fixing as the MC code emitter
// takes shape and the ARMCodeEmitter.cpp bits go away.
ShiftTypeShift = 4,
M_BitShift = 5,
ShiftImmShift = 5,
ShiftShift = 7,
N_BitShift = 7,
ImmHiShift = 8,
SoRotImmShift = 8,
RegRsShift = 8,
ExtRotImmShift = 10,
RegRdLoShift = 12,
RegRdShift = 12,
RegRdHiShift = 16,
RegRnShift = 16,
S_BitShift = 20,
W_BitShift = 21,
AM3_I_BitShift = 22,
D_BitShift = 22,
U_BitShift = 23,
P_BitShift = 24,
I_BitShift = 25,
CondShift = 28
};
}
class ARMBaseInstrInfo : public ARMGenInstrInfo {
const ARMSubtarget &Subtarget;

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -12,13 +12,13 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMFrameLowering.h"
#include "ARMInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"

2
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -14,12 +14,12 @@
#define DEBUG_TYPE "jit"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMConstantPoolValue.h"
#include "ARMInstrInfo.h"
#include "ARMRelocations.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -15,10 +15,10 @@
#define DEBUG_TYPE "arm-cp-islands"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMInstrInfo.h"
#include "Thumb2InstrInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"

2
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -16,11 +16,11 @@
#define DEBUG_TYPE "arm-pseudo"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"

2
lib/Target/ARM/ARMFastISel.cpp
View File

@ -14,13 +14,13 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMCallingConv.h"
#include "ARMRegisterInfo.h"
#include "ARMTargetMachine.h"
#include "ARMSubtarget.h"
#include "ARMConstantPoolValue.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CallingConv.h"
#include "llvm/DerivedTypes.h"
#include "llvm/GlobalVariable.h"

2
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -12,10 +12,10 @@
//===----------------------------------------------------------------------===//
#include "ARMFrameLowering.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"

22
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -14,8 +14,8 @@
#define DEBUG_TYPE "arm-isel"
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMAddressingModes.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
@ -373,7 +373,7 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
if (DisableShifterOp)
return false;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
// Don't match base register only case. That is matched to a separate
// lower complexity pattern with explicit register operand.
@ -489,7 +489,8 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
ARM_AM::ShiftOpc ShOpcVal =
ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
unsigned ShAmt = 0;
Base = N.getOperand(0);
@ -515,7 +516,7 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
// Try matching (R shl C) + (R).
if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
!(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't
// fold it.
@ -630,7 +631,8 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
ARM_AM::ShiftOpc ShOpcVal =
ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
unsigned ShAmt = 0;
Base = N.getOperand(0);
@ -656,7 +658,7 @@ AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
// Try matching (R shl C) + (R).
if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
!(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't
// fold it.
@ -701,7 +703,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
}
Offset = N;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
unsigned ShAmt = 0;
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't fold
@ -1079,7 +1081,7 @@ bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
if (DisableShifterOp)
return false;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
// Don't match base register only case. That is matched to a separate
// lower complexity pattern with explicit register operand.
@ -1220,9 +1222,9 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
OffReg = N.getOperand(1);
// Swap if it is ((R << c) + R).
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
if (ShOpcVal != ARM_AM::lsl) {
ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
if (ShOpcVal == ARM_AM::lsl)
std::swap(Base, OffReg);
}

5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -14,7 +14,6 @@
#define DEBUG_TYPE "arm-isel"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMISelLowering.h"
@ -24,6 +23,7 @@
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
@ -7351,7 +7351,8 @@ static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
if (Ptr->getOpcode() == ISD::ADD) {
isInc = true;
ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
ARM_AM::ShiftOpc ShOpcVal=
ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
if (ShOpcVal != ARM_AM::no_shift) {
Base = Ptr->getOperand(1);
Offset = Ptr->getOperand(0);

2
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -13,8 +13,8 @@
#include "ARMInstrInfo.h"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMMachineFunctionInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"

3
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -14,10 +14,10 @@
#define DEBUG_TYPE "arm-ldst-opt"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"

6
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -13,16 +13,16 @@
#define DEBUG_TYPE "mccodeemitter"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMFixupKinds.h"
#include "ARMInstrInfo.h"
#include "ARMMCExpr.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/raw_ostream.h"

2
lib/Target/ARM/ARMMCInstLower.cpp
View File

@ -14,7 +14,7 @@
#include "ARM.h"
#include "ARMAsmPrinter.h"
#include "ARMMCExpr.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/MC/MCExpr.h"

17
lib/Target/ARM/ARMSelectionDAGInfo.h
View File

@ -14,10 +14,27 @@
#ifndef ARMSELECTIONDAGINFO_H
#define ARMSELECTIONDAGINFO_H
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Target/TargetSelectionDAGInfo.h"
namespace llvm {
namespace ARM_AM {
static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
switch (Opcode) {
default: return ARM_AM::no_shift;
case ISD::SHL: return ARM_AM::lsl;
case ISD::SRL: return ARM_AM::lsr;
case ISD::SRA: return ARM_AM::asr;
case ISD::ROTR: return ARM_AM::ror;
//case ISD::ROTL: // Only if imm -> turn into ROTR.
// Can't handle RRX here, because it would require folding a flag into
// the addressing mode. :( This causes us to miss certain things.
//case ARMISD::RRX: return ARM_AM::rrx;
}
}
} // end namespace ARM_AM
class ARMSelectionDAGInfo : public TargetSelectionDAGInfo {
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.

4
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -8,10 +8,10 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMMCExpr.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"

1
lib/Target/ARM/CMakeLists.txt
View File

@ -34,7 +34,6 @@ add_llvm_target(ARMCodeGen
ARMJITInfo.cpp
ARMMachObjectWriter.cpp
ARMMCCodeEmitter.cpp
ARMMCExpr.cpp
ARMLoadStoreOptimizer.cpp
ARMMCInstLower.cpp
ARMRegisterInfo.cpp

6
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -16,8 +16,10 @@
#define DEBUG_TYPE "arm-disassembler"
#include "ARMDisassemblerCore.h"
#include "ARMAddressingModes.h"
#include "ARMMCExpr.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -14,7 +14,7 @@
#define DEBUG_TYPE "asm-printer"
#include "ARMBaseInfo.h"
#include "ARMInstPrinter.h"
#include "ARMAddressingModes.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"

15
lib/Target/ARM/ARMAddressingModes.h → lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
View File

@ -14,7 +14,6 @@
#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
@ -60,20 +59,6 @@ namespace ARM_AM {
}
}
static inline ShiftOpc getShiftOpcForNode(SDValue N) {
switch (N.getOpcode()) {
default: return ARM_AM::no_shift;
case ISD::SHL: return ARM_AM::lsl;
case ISD::SRL: return ARM_AM::lsr;
case ISD::SRA: return ARM_AM::asr;
case ISD::ROTR: return ARM_AM::ror;
//case ISD::ROTL: // Only if imm -> turn into ROTR.
// Can't handle RRX here, because it would require folding a flag into
// the addressing mode. :( This causes us to miss certain things.
//case ARMISD::RRX: return ARM_AM::rrx;
}
}
enum AMSubMode {
bad_am_submode = 0,
ia,

0
lib/Target/ARM/ARMMCExpr.cpp → lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
View File

0
lib/Target/ARM/ARMMCExpr.h → lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
View File

1
lib/Target/ARM/MCTargetDesc/CMakeLists.txt
View File

@ -1,6 +1,7 @@
add_llvm_library(LLVMARMDesc
ARMMCTargetDesc.cpp
ARMMCAsmInfo.cpp
ARMMCExpr.cpp
)
# Hack: we need to include 'main' target directory to grab private headers

2
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -13,12 +13,12 @@
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "Thumb1InstrInfo.h"
#include "Thumb1RegisterInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"

2
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -14,9 +14,9 @@
#include "Thumb2InstrInfo.h"
#include "ARM.h"
#include "ARMConstantPoolValue.h"
#include "ARMAddressingModes.h"
#include "ARMMachineFunctionInfo.h"
#include "Thumb2InstrInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"

2
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -9,11 +9,11 @@
#define DEBUG_TYPE "t2-reduce-size"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMBaseInstrInfo.h"
#include "ARMSubtarget.h"
#include "Thumb2InstrInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunctionPass.h"