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Hexagon: Add encoding bits to the TFR64 instructions.

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Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma 2013-03-05 18:42:28 +00:00
parent 62f38ca141
commit ee0ef13eba
3 changed files with 51 additions and 25 deletions
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66
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -251,28 +251,55 @@ multiclass TFR_base<string CextOp> {
}
}
class T_TFR64_Pred<bit PredNot, bit isPredNew>
: ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#
!if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
{
bits<5> dst;
bits<2> src1;
bits<5> src2;
let IClass = 0b1111;
let Inst{27-24} = 0b1101;
let Inst{13} = isPredNew;
let Inst{7} = PredNot;
let Inst{4-0} = dst;
let Inst{6-5} = src1;
let Inst{20-17} = src2{4-1};
let Inst{16} = 0b1;
let Inst{12-9} = src2{4-1};
let Inst{8} = 0b0;
}
multiclass TFR64_Pred<bit PredNot> {
let PredSense = !if(PredNot, "false", "true") in {
def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
def _c#NAME : T_TFR64_Pred<PredNot, 0>;
let PNewValue = "new" in
def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
}
}
let InputType = "reg", neverHasSideEffects = 1 in
multiclass TFR64_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let neverHasSideEffects = 1 in
multiclass TFR64_base<string BaseName> {
let BaseOpcode = BaseName in {
let isPredicable = 1 in
def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
"$dst = $src1",
[]>;
def NAME : ALU32Inst <(outs DoubleRegs:$dst),
(ins DoubleRegs:$src1),
"$dst = $src1" > {
bits<5> dst;
bits<5> src1;
let IClass = 0b1111;
let Inst{27-23} = 0b01010;
let Inst{4-0} = dst;
let Inst{20-17} = src1{4-1};
let Inst{16} = 0b1;
let Inst{12-9} = src1{4-1};
let Inst{8} = 0b0;
}
let isPredicated = 1 in {
defm Pt : TFR64_Pred<0>;
@ -281,9 +308,8 @@ multiclass TFR64_base<string CextOp> {
}
}
multiclass TFRI_Pred<bit PredNot> {
let PredSense = !if(PredNot, "false", "true") in {
let isMoveImm = 1, PredSense = !if(PredNot, "false", "true") in {
def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
@ -301,8 +327,8 @@ multiclass TFRI_Pred<bit PredNot> {
let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
multiclass TFRI_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
isReMaterializable = 1 in
let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
"$dst = #$src1",
[(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
@ -317,7 +343,7 @@ multiclass TFRI_base<string CextOp> {
defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
defm TFR64 : TFR64_base<"TFR64">, ImmRegRel, PredNewRel;
defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
// Transfer control register.
let neverHasSideEffects = 1 in

4
test/CodeGen/Hexagon/args.ll
View File

@ -1,11 +1,11 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
; CHECK: r5 = #6
; CHECK: r0 = #1
; CHECK: r1 = #2
; CHECK: r2 = #3
; CHECK: r3 = #4
; CHECK: r4 = #5
; CHECK: r5 = #6
define void @foo() nounwind {

6
test/CodeGen/Hexagon/dualstore.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
; Check that we generate dual stores in one packet in V4
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000
; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000
; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000
; CHECK-NEXT: }
@Reg = global i32 0, align 4