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implement rdar://8407928 - support for in/out with a missing "a" register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-09-11 16:32:12 +00:00
parent cbf8a98c7c
commit ee211d0ed6
2 changed files with 45 additions and 1 deletions
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34
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -811,7 +811,8 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
if (getLexer().is(AsmToken::EndOfStatement))
Parser.Lex(); // Consume the EndOfStatement
// FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
// FIXME: Hack to handle recognize s{hr,ar,hl} <op>, $1. Canonicalize to
// "shift <op>".
if ((Name.startswith("shr") || Name.startswith("sar") ||
Name.startswith("shl")) &&
Operands.size() == 3) {
@ -823,6 +824,37 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
}
}
// FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
// "inb <op>, %al".
if ((Name == "inb" || Name == "inw" || Name == "inl") &&
Operands.size() == 2) {
unsigned Reg;
if (Name[2] == 'b')
Reg = MatchRegisterName("al");
else if (Name[2] == 'w')
Reg = MatchRegisterName("ax");
else
Reg = MatchRegisterName("eax");
SMLoc Loc = Operands.back()->getEndLoc();
Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
}
// FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
// "outb %al, <op>".
if ((Name == "outb" || Name == "outw" || Name == "outl") &&
Operands.size() == 2) {
unsigned Reg;
if (Name[3] == 'b')
Reg = MatchRegisterName("al");
else if (Name[3] == 'w')
Reg = MatchRegisterName("ax");
else
Reg = MatchRegisterName("eax");
SMLoc Loc = Operands.back()->getEndLoc();
Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
std::swap(Operands[1], Operands[2]);
}
// FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
// "f{mul*,add*,sub*,div*} $op"
if ((Name.startswith("fmul") || Name.startswith("fadd") ||

12
test/MC/AsmParser/X86/x86_instructions.s
View File

@ -188,3 +188,15 @@ cmovnz %bx, %ax
// CHECK: cmovneq %rbx, %rax
cmovnzq %rbx, %rax
// rdar://8407928
// CHECK: inb $127, %al
// CHECK: inw %dx, %ax
// CHECK: outb %al, $127
// CHECK: outw %ax, %dx
// CHECK: inl %dx, %eax
inb $0x7f
inw %dx
outb $0x7f
outw %dx
inl %dx