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Thumb2 assembly parsing and encoding for STR.

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More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-09-16 21:55:56 +00:00
parent 4e0a55d0d1
commit ee2c2a4f98
3 changed files with 74 additions and 21 deletions
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lib/Target/ARM/ARMISelLowering.cpp
+13
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@@ -5495,6 +5495,19 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MI->dump();
llvm_unreachable("Unexpected instr type to insert");
}
// The Thumb2 pre-indexed stores have the same MI operands, they just
// define them differently in the .td files from the isel patterns, so
// they need pseudos.
case ARM::t2STR_preidx:
MI->setDesc(TII->get(ARM::t2STR_PRE));
return BB;
case ARM::t2STRB_preidx:
MI->setDesc(TII->get(ARM::t2STRB_PRE));
return BB;
case ARM::t2STRH_preidx:
MI->setDesc(TII->get(ARM::t2STRH_PRE));
return BB;
case ARM::STRi_preidx:
case ARM::STRBi_preidx: {
unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?