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Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1102,7 +1102,8 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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}
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}
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// Load, store, and memory fence
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// Load, store, and memory fence
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def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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TB, Requires<[HasSSE1]>;
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// MXCSR register
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// MXCSR register
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def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
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def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
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@ -1,5 +1,8 @@
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// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
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// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
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sfence
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// CHECK: sfence
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// CHECK: encoding: [0x0f,0xae,0xf8]
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lfence
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lfence
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// CHECK: lfence
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// CHECK: lfence
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// CHECK: encoding: [0x0f,0xae,0xe8]
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// CHECK: encoding: [0x0f,0xae,0xe8]
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