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synced 2024-08-23 17:29:19 +00:00
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138437 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,7 +51,7 @@ using namespace llvm;
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/// explicitly nulled out.
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void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
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assert(isReg() && "Can only add reg operand to use lists");
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// If the reginfo pointer is null, just explicitly null out or next/prev
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// pointers, to ensure they are not garbage.
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if (RegInfo == 0) {
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@ -59,23 +59,23 @@ void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
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Contents.Reg.Next = 0;
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return;
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}
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// Otherwise, add this operand to the head of the registers use/def list.
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MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
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// For SSA values, we prefer to keep the definition at the start of the list.
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// we do this by skipping over the definition if it is at the head of the
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// list.
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if (*Head && (*Head)->isDef())
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Head = &(*Head)->Contents.Reg.Next;
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Contents.Reg.Next = *Head;
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if (Contents.Reg.Next) {
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assert(getReg() == Contents.Reg.Next->getReg() &&
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"Different regs on the same list!");
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Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
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}
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Contents.Reg.Prev = Head;
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*Head = this;
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}
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@ -86,7 +86,7 @@ void MachineOperand::RemoveRegOperandFromRegInfo() {
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assert(isOnRegUseList() && "Reg operand is not on a use list");
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// Unlink this from the doubly linked list of operands.
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MachineOperand *NextOp = Contents.Reg.Next;
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*Contents.Reg.Prev = NextOp;
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*Contents.Reg.Prev = NextOp;
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if (NextOp) {
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assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
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NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
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@ -97,7 +97,7 @@ void MachineOperand::RemoveRegOperandFromRegInfo() {
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void MachineOperand::setReg(unsigned Reg) {
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if (getReg() == Reg) return; // No change.
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// Otherwise, we have to change the register. If this operand is embedded
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// into a machine function, we need to update the old and new register's
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// use/def lists.
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@ -109,7 +109,7 @@ void MachineOperand::setReg(unsigned Reg) {
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AddRegOperandToRegInfo(&MF->getRegInfo());
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return;
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}
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// Otherwise, just change the register, no problem. :)
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SmallContents.RegNo = Reg;
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}
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@ -144,7 +144,7 @@ void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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if (isReg() && getParent() && getParent()->getParent() &&
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getParent()->getParent()->getParent())
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RemoveRegOperandFromRegInfo();
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OpKind = MO_Immediate;
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Contents.ImmVal = ImmVal;
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}
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@ -155,7 +155,7 @@ void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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bool isKill, bool isDead, bool isUndef,
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bool isDebug) {
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// If this operand is already a register operand, use setReg to update the
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// If this operand is already a register operand, use setReg to update the
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// register's use/def lists.
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if (isReg()) {
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assert(!isEarlyClobber());
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@ -189,7 +189,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType() ||
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getTargetFlags() != Other.getTargetFlags())
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return false;
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switch (getType()) {
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default: llvm_unreachable("Unrecognized operand type");
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case MachineOperand::MO_Register:
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@ -322,7 +322,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
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default:
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llvm_unreachable("Unrecognized operand type");
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}
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if (unsigned TF = getTargetFlags())
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OS << "[TF=" << TF << ']';
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}
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@ -408,7 +408,7 @@ uint64_t MachineMemOperand::getAlignment() const {
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raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
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assert((MMO.isLoad() || MMO.isStore()) &&
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"SV has to be a load, store or both.");
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if (MMO.isVolatile())
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OS << "Volatile ";
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@ -417,7 +417,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
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if (MMO.isStore())
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OS << "ST";
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OS << MMO.getSize();
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// Print the address information.
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OS << "[";
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if (!MMO.getValue())
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@ -510,7 +510,7 @@ MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
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}
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/// MachineInstr ctor - Work exactly the same as the ctor two above, except
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/// that the MachineInstr is created and added to the end of the specified
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/// that the MachineInstr is created and added to the end of the specified
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/// basic block.
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
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: MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
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@ -605,7 +605,7 @@ void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
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/// addOperand - Add the specified operand to the instruction. If it is an
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/// implicit operand, it is added to the end of the operand list. If it is
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/// an explicit operand it is added at the end of the explicit operand list
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/// (before the first implicit operand).
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/// (before the first implicit operand).
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void MachineInstr::addOperand(const MachineOperand &Op) {
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bool isImpReg = Op.isReg() && Op.isImplicit();
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assert((isImpReg || !OperandsComplete()) &&
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@ -620,10 +620,10 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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// reallocate.
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if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
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Operands.push_back(Op);
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// Set the parent of the operand.
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Operands.back().ParentMI = this;
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// If the operand is a register, update the operand's use list.
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if (Op.isReg()) {
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Operands.back().AddRegOperandToRegInfo(RegInfo);
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@ -635,7 +635,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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return;
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}
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}
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// Otherwise, we have to insert a real operand before any implicit ones.
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unsigned OpNo = Operands.size()-NumImplicitOps;
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@ -660,7 +660,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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// list, add the operand, then add the register operands back to their use
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// list. This also must handle the case when the operand list reallocates
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// to somewhere else.
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// If insertion of this operand won't cause reallocation of the operand
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// list, just remove the implicit operands, add the operand, then re-add all
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// the rest of the operands.
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@ -668,7 +668,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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assert(Operands[i].isReg() && "Should only be an implicit reg!");
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Operands[i].RemoveRegOperandFromRegInfo();
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}
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// Add the operand. If it is a register, add it to the reg list.
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Operands.insert(Operands.begin()+OpNo, Op);
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Operands[OpNo].ParentMI = this;
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@ -679,7 +679,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
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Operands[OpNo].setIsEarlyClobber(true);
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}
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// Re-add all the implicit ops.
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for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
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assert(Operands[i].isReg() && "Should only be an implicit reg!");
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@ -690,10 +690,10 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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// operands from their list, then readd them after the operand list is
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// reallocated.
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RemoveRegOperandsFromUseLists();
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Operands.insert(Operands.begin()+OpNo, Op);
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Operands[OpNo].ParentMI = this;
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// Re-add all the operands.
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AddRegOperandsToUseLists(*RegInfo);
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@ -709,13 +709,13 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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///
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void MachineInstr::RemoveOperand(unsigned OpNo) {
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assert(OpNo < Operands.size() && "Invalid operand number");
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// Special case removing the last one.
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if (OpNo == Operands.size()-1) {
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// If needed, remove from the reg def/use list.
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if (Operands.back().isReg() && Operands.back().isOnRegUseList())
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Operands.back().RemoveRegOperandFromRegInfo();
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Operands.pop_back();
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return;
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}
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@ -730,7 +730,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) {
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Operands[i].RemoveRegOperandFromRegInfo();
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}
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}
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Operands.erase(Operands.begin()+OpNo);
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if (RegInfo) {
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@ -951,7 +951,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
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return -1;
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}
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/// isRegTiedToUseOperand - Given the index of a register def operand,
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/// check if the register def is tied to a source operand, due to either
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/// two-address elimination or inline assembly constraints. Returns the
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@ -1212,7 +1212,7 @@ bool MachineInstr::hasVolatileMemoryRef() const {
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// conservatively assume it wasn't preserved.
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if (memoperands_empty())
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return true;
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// Check the memory reference information for volatile references.
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for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
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if ((*I)->isVolatile())
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@ -1319,7 +1319,7 @@ void MachineInstr::dump() const {
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dbgs() << " " << *this;
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}
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static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
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static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
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raw_ostream &CommentOS) {
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const LLVMContext &Ctx = MF->getFunction()->getContext();
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if (!DL.isUnknown()) { // Print source line info.
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@ -1640,7 +1640,7 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
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// new implicit operand if required.
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if (Found || !AddIfNotFound)
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return Found;
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addOperand(MachineOperand::CreateReg(IncomingReg,
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true /*IsDef*/,
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true /*IsImp*/,
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