From ee64be9c176a21a6fd86d2c4eebda571f872d4a2 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Thu, 8 Sep 2011 22:17:35 +0000 Subject: [PATCH] Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index cf90490703e..171349c0663 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -920,7 +920,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::VSELECT, MVT::v2f64, Custom); setOperationAction(ISD::VSELECT, MVT::v2i64, Custom); setOperationAction(ISD::VSELECT, MVT::v16i8, Custom); - setOperationAction(ISD::VSELECT, MVT::v8i16, Custom); setOperationAction(ISD::VSELECT, MVT::v4i32, Custom); setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); @@ -8703,16 +8702,20 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { assert(Op2.getValueType().isVector() && "Op2 must be a vector"); assert(Cond.getValueType().isVector() && "Cond must be a vector"); assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch"); - - switch (Op1.getValueType().getSimpleVT().SimpleTy) { + + EVT VT = Op1.getValueType(); + switch (VT.getSimpleVT().SimpleTy) { default: break; - case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops)); - case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops)); - case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops)); - case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops)); - case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops)); + case MVT::v2i64: + case MVT::v2f64: + return DAG.getNode(X86ISD::BLENDVPD, DL, VT, Ops, array_lengthof(Ops)); + case MVT::v4i32: + case MVT::v4f32: + return DAG.getNode(X86ISD::BLENDVPS, DL, VT , Ops, array_lengthof(Ops)); + case MVT::v16i8: + return DAG.getNode(X86ISD::PBLENDVB, DL, VT , Ops, array_lengthof(Ops)); } - + return SDValue(); }