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Merging r199832:

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r199832 | rafael.espindola | 2014-01-22 15:20:52 -0500 (Wed, 22 Jan 2014) | 11 lines

Fix pr18515.

My understanding (from reading just the llvm code) is that
* most ppc cpus have a "sync n" instruction and an msync alias that is
* "sync 0".
* "book e" cpus instead have a msync instruction and not the more
general "sync n"

This patch reflects that in the .td files, allowing a single codepath
for
asm ond obj streamer and incidentelly fixes a crash when EmitRawText was
called on a obj streamer.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-04-09 00:20:45 +00:00
parent da282fcf6a
commit ee6825dc5c
2 changed files with 18 additions and 14 deletions
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7
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -701,13 +701,6 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return; return;
} }
break; break;
case PPC::SYNC:
// In Book E sync is called msync, handle this special case here...
if (Subtarget.isBookE()) {
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
break;
case PPC::LD: case PPC::LD:
case PPC::STD: case PPC::STD:
case PPC::LWA_32: case PPC::LWA_32:

25
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -580,6 +580,7 @@ def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
def IsBookE : Predicate<"PPCSubTarget.isBookE()">; def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions. // PowerPC Multiclass Definitions.
@ -1541,8 +1542,17 @@ def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
"stmw $rS, $dst", LdStLMW, []>; "stmw $rS, $dst", LdStLMW, []>;
def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
"sync $L", LdStSync, []>; "sync $L", LdStSync, []>, Requires<[IsNotBookE]>;
def : Pat<(int_ppc_sync), (SYNC 0)>;
let isCodeGenOnly = 1 in {
def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
"msync", LdStSync, []>, Requires<[IsBookE]> {
let L = 0;
}
}
def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PPC32 Arithmetic Instructions. // PPC32 Arithmetic Instructions.
@ -2284,7 +2294,8 @@ def : Pat<(f64 (extloadf32 xaddr:$src)),
def : Pat<(f64 (fextend f32:$src)), def : Pat<(f64 (fextend f32:$src)),
(COPY_TO_REGCLASS $src, F8RC)>; (COPY_TO_REGCLASS $src, F8RC)>;
def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>; def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
// Additional FNMSUB patterns: -a*c + b == -(a*c - b) // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
@ -2373,10 +2384,10 @@ class PPCAsmPseudo<string asm, dag iops>
def : InstAlias<"sc", (SC 0)>; def : InstAlias<"sc", (SC 0)>;
def : InstAlias<"sync", (SYNC 0)>; def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
def : InstAlias<"msync", (SYNC 0)>; def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
def : InstAlias<"lwsync", (SYNC 1)>; def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
def : InstAlias<"ptesync", (SYNC 2)>; def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
def : InstAlias<"wait", (WAIT 0)>; def : InstAlias<"wait", (WAIT 0)>;
def : InstAlias<"waitrsv", (WAIT 1)>; def : InstAlias<"waitrsv", (WAIT 1)>;