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Fix PR15267
- When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
9b5b8b0b94
commit
eedff3547d
@ -363,30 +363,135 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
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EVT SrcVT = LD->getMemoryVT();
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ISD::LoadExtType ExtType = LD->getExtensionType();
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SmallVector<SDValue, 8> LoadVals;
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SmallVector<SDValue, 8> Vals;
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SmallVector<SDValue, 8> LoadChains;
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unsigned NumElem = SrcVT.getVectorNumElements();
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
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Op.getNode()->getValueType(0).getScalarType(),
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Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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EVT SrcEltVT = SrcVT.getScalarType();
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EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
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// When elements in a vector is not byte-addressable, we cannot directly
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// load each element by advancing pointer, which could only address bytes.
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// Instead, we load all significant words, mask bits off, and concatenate
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// them to form each element. Finally, they are extended to destination
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// scalar type to build the destination vector.
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EVT WideVT = TLI.getPointerTy();
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LoadVals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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assert(WideVT.isRound() &&
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"Could not handle the sophisticated case when the widest integer is"
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" not power of 2.");
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assert(WideVT.bitsGE(SrcEltVT) &&
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"Type is not legalized?");
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unsigned WideBytes = WideVT.getStoreSize();
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unsigned Offset = 0;
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unsigned RemainingBytes = SrcVT.getStoreSize();
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SmallVector<SDValue, 8> LoadVals;
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while (RemainingBytes > 0) {
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SDValue ScalarLoad;
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unsigned LoadBytes = WideBytes;
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if (RemainingBytes >= LoadBytes) {
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ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
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LD->getPointerInfo().getWithOffset(Offset),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isInvariant(), LD->getAlignment());
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} else {
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EVT LoadVT = WideVT;
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while (RemainingBytes < LoadBytes) {
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LoadBytes >>= 1; // Reduce the load size by half.
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LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
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}
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ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
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LD->getPointerInfo().getWithOffset(Offset),
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LoadVT, LD->isVolatile(),
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LD->isNonTemporal(), LD->getAlignment());
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}
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RemainingBytes -= LoadBytes;
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Offset += LoadBytes;
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(LoadBytes));
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LoadVals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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// Extract bits, pack and extend/trunc them into destination type.
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unsigned SrcEltBits = SrcEltVT.getSizeInBits();
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SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
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unsigned BitOffset = 0;
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unsigned WideIdx = 0;
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unsigned WideBits = WideVT.getSizeInBits();
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for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
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SDValue Lo, Hi, ShAmt;
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if (BitOffset < WideBits) {
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ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
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Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
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Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
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}
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BitOffset += SrcEltBits;
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if (BitOffset >= WideBits) {
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WideIdx++;
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Offset -= WideBits;
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if (Offset > 0) {
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ShAmt = DAG.getConstant(SrcEltBits - Offset,
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TLI.getShiftAmountTy(WideVT));
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Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
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Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
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}
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}
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if (Hi.getNode())
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Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
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switch (ExtType) {
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default: llvm_unreachable("Unknown extended-load op!");
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case ISD::EXTLOAD:
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Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
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break;
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case ISD::ZEXTLOAD:
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Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
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break;
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case ISD::SEXTLOAD:
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ShAmt = DAG.getConstant(WideBits - SrcEltBits,
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TLI.getShiftAmountTy(WideVT));
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Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
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Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
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Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
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break;
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}
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Vals.push_back(Lo);
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}
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} else {
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unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
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for (unsigned Idx=0; Idx<NumElem; Idx++) {
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SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
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Op.getNode()->getValueType(0).getScalarType(),
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Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
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SrcVT.getScalarType(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
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DAG.getIntPtrConstant(Stride));
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Vals.push_back(ScalarLoad.getValue(0));
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LoadChains.push_back(ScalarLoad.getValue(1));
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}
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}
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&LoadChains[0], LoadChains.size());
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SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
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Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size());
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Op.getNode()->getValueType(0), &Vals[0], Vals.size());
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AddLegalizedOperand(Op.getValue(0), Value);
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AddLegalizedOperand(Op.getValue(1), NewChain);
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66
test/CodeGen/X86/pr15267.ll
Normal file
66
test/CodeGen/X86/pr15267.ll
Normal file
@ -0,0 +1,66 @@
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
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define <4 x i3> @test1(<4 x i3>* %in) nounwind {
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%ret = load <4 x i3>* %in, align 1
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ret <4 x i3> %ret
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}
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; CHECK: test1
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; CHECK: movzwl
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; CHECK: shrl $3
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; CHECK: andl $7
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; CHECK: andl $7
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $6
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; CHECK: andl $7
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; CHECK: pinsrd $2
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; CHECK: shrl $9
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; CHECK: andl $7
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i1> @test2(<4 x i1>* %in) nounwind {
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%ret = load <4 x i1>* %in, align 1
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ret <4 x i1> %ret
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}
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; CHECK: test2
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; CHECK: movzbl
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; CHECK: shrl
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; CHECK: andl $1
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; CHECK: andl $1
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $2
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; CHECK: andl $1
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; CHECK: pinsrd $2
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; CHECK: shrl $3
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; CHECK: andl $1
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i64> @test3(<4 x i1>* %in) nounwind {
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%wide.load35 = load <4 x i1>* %in, align 1
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%sext = sext <4 x i1> %wide.load35 to <4 x i64>
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ret <4 x i64> %sext
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}
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; CHECK: test3
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; CHECK: movzbl
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; CHECK: shrl
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; CHECK: andl $1
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; CHECK: andl $1
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $2
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; CHECK: andl $1
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; CHECK: pinsrd $2
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; CHECK: shrl $3
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; CHECK: andl $1
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; CHECK: pinsrd $3
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; CHECK: pslld
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; CHECK: psrad
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; CHECK: pmovsxdq
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; CHECK: pmovsxdq
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; CHECK: ret
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