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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
[X86][SSE] Added nounwind attribute to vector shift tests.
Stop i686 codegen from generating cfi directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242443 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -10,7 +10,7 @@
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; Variable Shifts
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;
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define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
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; SSE2-LABEL: var_shift_v2i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd %xmm0, %rax
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@ -56,25 +56,9 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; X32-SSE-LABEL: var_shift_v2i64:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: pushl %ebp
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; X32-SSE-NEXT: .Ltmp0:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE-NEXT: pushl %ebx
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; X32-SSE-NEXT: .Ltmp1:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE-NEXT: pushl %edi
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; X32-SSE-NEXT: .Ltmp2:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 16
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; X32-SSE-NEXT: pushl %esi
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; X32-SSE-NEXT: .Ltmp3:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 20
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; X32-SSE-NEXT: .Ltmp4:
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; X32-SSE-NEXT: .cfi_offset %esi, -20
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; X32-SSE-NEXT: .Ltmp5:
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; X32-SSE-NEXT: .cfi_offset %edi, -16
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; X32-SSE-NEXT: .Ltmp6:
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; X32-SSE-NEXT: .cfi_offset %ebx, -12
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; X32-SSE-NEXT: .Ltmp7:
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; X32-SSE-NEXT: .cfi_offset %ebp, -8
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; X32-SSE-NEXT: movd %xmm2, %edx
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
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@ -117,7 +101,7 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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ret <2 x i64> %shift
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}
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define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
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define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; SSE2-LABEL: var_shift_v4i32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movdqa %xmm1, %xmm2
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@ -211,7 +195,7 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
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ret <4 x i32> %shift
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}
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define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
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define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
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; SSE2-LABEL: var_shift_v8i16:
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; SSE2: # BB#0:
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; SSE2-NEXT: psllw $12, %xmm1
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@ -343,7 +327,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
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ret <8 x i16> %shift
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}
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define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
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define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; SSE2-LABEL: var_shift_v16i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
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@ -531,7 +515,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; Uniform Variable Shifts
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;
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define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
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; SSE2-LABEL: splatvar_shift_v2i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,0,1]
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@ -594,25 +578,9 @@ define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; X32-SSE-LABEL: splatvar_shift_v2i64:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: pushl %ebp
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; X32-SSE-NEXT: .Ltmp8:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE-NEXT: pushl %ebx
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; X32-SSE-NEXT: .Ltmp9:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE-NEXT: pushl %edi
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; X32-SSE-NEXT: .Ltmp10:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 16
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; X32-SSE-NEXT: pushl %esi
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; X32-SSE-NEXT: .Ltmp11:
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; X32-SSE-NEXT: .cfi_def_cfa_offset 20
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; X32-SSE-NEXT: .Ltmp12:
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; X32-SSE-NEXT: .cfi_offset %esi, -20
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; X32-SSE-NEXT: .Ltmp13:
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; X32-SSE-NEXT: .cfi_offset %edi, -16
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; X32-SSE-NEXT: .Ltmp14:
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; X32-SSE-NEXT: .cfi_offset %ebx, -12
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; X32-SSE-NEXT: .Ltmp15:
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; X32-SSE-NEXT: .cfi_offset %ebp, -8
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; X32-SSE-NEXT: movd %xmm2, %edx
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@ -657,7 +625,7 @@ define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
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ret <2 x i64> %shift
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}
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define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
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define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; SSE2-LABEL: splatvar_shift_v4i32:
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; SSE2: # BB#0:
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; SSE2-NEXT: xorps %xmm2, %xmm2
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@ -690,7 +658,7 @@ define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
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ret <4 x i32> %shift
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}
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define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
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define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
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; SSE2-LABEL: splatvar_shift_v8i16:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd %xmm1, %eax
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@ -725,7 +693,7 @@ define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
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ret <8 x i16> %shift
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}
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define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
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define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; SSE2-LABEL: splatvar_shift_v16i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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@ -955,7 +923,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; Constant Shifts
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;
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define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
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define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
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; SSE2-LABEL: constant_shift_v2i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: movd %xmm0, %rax
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@ -1016,7 +984,7 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
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ret <2 x i64> %shift
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}
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define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
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define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
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; SSE2-LABEL: constant_shift_v4i32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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@ -1082,7 +1050,7 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
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ret <4 x i32> %shift
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}
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define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
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define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
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; SSE2-LABEL: constant_shift_v8i16:
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; SSE2: # BB#0:
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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@ -1168,7 +1136,7 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
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ret <8 x i16> %shift
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}
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define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
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define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
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; SSE2-LABEL: constant_shift_v16i8:
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; SSE2: # BB#0:
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; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
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@ -1360,7 +1328,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
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; Uniform Constant Shifts
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;
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define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
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define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
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; SSE2-LABEL: splatconstant_shift_v2i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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@ -1406,7 +1374,7 @@ define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
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ret <2 x i64> %shift
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}
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define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
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define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
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; SSE-LABEL: splatconstant_shift_v4i32:
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; SSE: # BB#0:
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; SSE-NEXT: psrad $5, %xmm0
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@ -1425,7 +1393,7 @@ define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
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ret <4 x i32> %shift
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}
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define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
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define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
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; SSE-LABEL: splatconstant_shift_v8i16:
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; SSE: # BB#0:
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; SSE-NEXT: psraw $3, %xmm0
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@ -1444,7 +1412,7 @@ define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
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ret <8 x i16> %shift
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}
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define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
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define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
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; SSE-LABEL: splatconstant_shift_v16i8:
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; SSE: # BB#0:
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; SSE-NEXT: psrlw $3, %xmm0
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@ -5,7 +5,7 @@
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; Variable Shifts
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;
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define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
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define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
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; AVX1-LABEL: var_shift_v4i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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@ -59,7 +59,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
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ret <4 x i64> %shift
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}
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define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
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define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
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; AVX1-LABEL: var_shift_v8i32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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@ -98,7 +98,7 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
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ret <8 x i32> %shift
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}
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define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
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define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
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; AVX1-LABEL: var_shift_v16i16:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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@ -151,7 +151,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
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ret <16 x i16> %shift
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}
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define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
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define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
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; AVX1-LABEL: var_shift_v32i8:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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@ -242,7 +242,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
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; Uniform Variable Shifts
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;
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define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
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define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
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; AVX1-LABEL: splatvar_shift_v4i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
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@ -300,7 +300,7 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
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ret <4 x i64> %shift
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}
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define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
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define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
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; AVX1-LABEL: splatvar_shift_v8i32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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@ -322,7 +322,7 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
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ret <8 x i32> %shift
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}
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define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
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define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
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; AVX1-LABEL: splatvar_shift_v16i16:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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@ -346,7 +346,7 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
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ret <16 x i16> %shift
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}
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define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
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define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
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; AVX1-LABEL: splatvar_shift_v32i8:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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@ -433,7 +433,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
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; Constant Shifts
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;
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define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
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define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
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; AVX1-LABEL: constant_shift_v4i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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@ -477,7 +477,7 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
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ret <4 x i64> %shift
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}
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define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
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define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
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; AVX1-LABEL: constant_shift_v8i32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpsrad $7, %xmm0, %xmm1
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@ -504,7 +504,7 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
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ret <8 x i32> %shift
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||||
}
|
||||
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -553,7 +553,7 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
|
||||
@ -638,7 +638,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
; Uniform Constant Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -661,7 +661,7 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsrad $5, %xmm0, %xmm1
|
||||
@ -678,7 +678,7 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsraw $3, %xmm0, %xmm1
|
||||
@ -695,7 +695,7 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
|
@ -10,7 +10,7 @@
|
||||
; Variable Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v2i64:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
|
||||
@ -57,7 +57,7 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
||||
@ -151,7 +151,7 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v8i16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: psllw $12, %xmm1
|
||||
@ -283,7 +283,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: psllw $5, %xmm1
|
||||
@ -393,7 +393,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
; Uniform Variable Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
||||
; SSE-LABEL: splatvar_shift_v2i64:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psrlq %xmm1, %xmm0
|
||||
@ -414,7 +414,7 @@ define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: xorps %xmm2, %xmm2
|
||||
@ -447,7 +447,7 @@ define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v8i16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movd %xmm1, %eax
|
||||
@ -482,7 +482,7 @@ define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
@ -623,7 +623,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
; Constant Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
|
||||
define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v2i64:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
@ -669,7 +669,7 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
|
||||
define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
@ -735,7 +735,7 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
|
||||
define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v8i16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
@ -821,7 +821,7 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
|
||||
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
|
||||
@ -932,7 +932,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
|
||||
; Uniform Constant Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
|
||||
define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v2i64:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psrlq $7, %xmm0
|
||||
@ -951,7 +951,7 @@ define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
|
||||
define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v4i32:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psrld $5, %xmm0
|
||||
@ -970,7 +970,7 @@ define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
|
||||
define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v8i16:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psrlw $3, %xmm0
|
||||
@ -989,7 +989,7 @@ define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
|
||||
define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v16i8:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psrlw $3, %xmm0
|
||||
|
@ -5,7 +5,7 @@
|
||||
; Variable Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
@ -29,7 +29,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -68,7 +68,7 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
@ -121,7 +121,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -179,7 +179,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
; Uniform Variable Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -197,7 +197,7 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
@ -219,7 +219,7 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -243,7 +243,7 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
@ -301,7 +301,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
; Constant Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
|
||||
define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -322,7 +322,7 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
|
||||
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsrld $7, %xmm0, %xmm1
|
||||
@ -349,7 +349,7 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -398,7 +398,7 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -454,7 +454,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
; Uniform Constant Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm1
|
||||
@ -471,7 +471,7 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsrld $5, %xmm0, %xmm1
|
||||
@ -488,7 +488,7 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm1
|
||||
@ -505,7 +505,7 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
|
@ -10,7 +10,7 @@
|
||||
; Variable Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v2i64:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
|
||||
@ -57,7 +57,7 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pslld $23, %xmm1
|
||||
@ -112,7 +112,7 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v8i16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: psllw $12, %xmm1
|
||||
@ -244,7 +244,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; SSE2-LABEL: var_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: psllw $5, %xmm1
|
||||
@ -350,7 +350,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
; Uniform Variable Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
||||
; SSE-LABEL: splatvar_shift_v2i64:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psllq %xmm1, %xmm0
|
||||
@ -371,7 +371,7 @@ define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: xorps %xmm2, %xmm2
|
||||
@ -404,7 +404,7 @@ define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v8i16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movd %xmm1, %eax
|
||||
@ -439,7 +439,7 @@ define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; SSE2-LABEL: splatvar_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
@ -575,7 +575,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
|
||||
; Constant Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
|
||||
define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v2i64:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
@ -621,7 +621,7 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
|
||||
define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v4i32:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,32,64,128]
|
||||
@ -664,7 +664,7 @@ define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
|
||||
define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
|
||||
; SSE-LABEL: constant_shift_v8i16:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
|
||||
@ -683,7 +683,7 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
|
||||
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; SSE2-LABEL: constant_shift_v16i8:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
|
||||
@ -790,7 +790,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
|
||||
; Uniform Constant Shifts
|
||||
;
|
||||
|
||||
define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
|
||||
define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v2i64:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psllq $7, %xmm0
|
||||
@ -809,7 +809,7 @@ define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
||||
define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
|
||||
define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v4i32:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pslld $5, %xmm0
|
||||
@ -828,7 +828,7 @@ define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
|
||||
ret <4 x i32> %shift
|
||||
}
|
||||
|
||||
define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
|
||||
define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v8i16:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psllw $3, %xmm0
|
||||
@ -847,7 +847,7 @@ define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
|
||||
ret <8 x i16> %shift
|
||||
}
|
||||
|
||||
define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
|
||||
define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; SSE-LABEL: splatconstant_shift_v16i8:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: psllw $3, %xmm0
|
||||
|
@ -5,7 +5,7 @@
|
||||
; Variable Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
@ -29,7 +29,7 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
@ -54,7 +54,7 @@ define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
@ -107,7 +107,7 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
|
||||
; AVX1-LABEL: var_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -161,7 +161,7 @@ define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
; Uniform Variable Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -179,7 +179,7 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
@ -201,7 +201,7 @@ define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
@ -225,7 +225,7 @@ define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
|
||||
; AVX1-LABEL: splatvar_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
@ -279,7 +279,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
|
||||
; Constant Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
|
||||
define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -300,7 +300,7 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
|
||||
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm1
|
||||
@ -317,7 +317,7 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
|
||||
@ -334,7 +334,7 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: constant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
@ -386,7 +386,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
|
||||
; Uniform Constant Shifts
|
||||
;
|
||||
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v4i64:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsllq $7, %xmm0, %xmm1
|
||||
@ -403,7 +403,7 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
|
||||
ret <4 x i64> %shift
|
||||
}
|
||||
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v8i32:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpslld $5, %xmm0, %xmm1
|
||||
@ -420,7 +420,7 @@ define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
|
||||
ret <8 x i32> %shift
|
||||
}
|
||||
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v16i16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpsllw $3, %xmm0, %xmm1
|
||||
@ -437,7 +437,7 @@ define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
|
||||
ret <16 x i16> %shift
|
||||
}
|
||||
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
|
||||
define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
|
||||
; AVX1-LABEL: splatconstant_shift_v32i8:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
|
||||
|
Loading…
Reference in New Issue
Block a user