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Push ops list, asm string, and pattern all the way up to InstV8. Move the
InstV8 class to the InstrFormats file where it belongs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7,11 +7,26 @@
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//
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//===----------------------------------------------------------------------===//
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class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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// Format 2 instructions
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class F2<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern> {
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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@ -21,27 +36,20 @@ class F2 : InstV8 { // Format 2 instructions
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
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class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
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: F2<ops, asmstr, pattern> {
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bits<5> rd;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op2 = op2Val;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
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list<dag> pattern> : F2 {
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list<dag> pattern> : F2<ops, asmstr, pattern> {
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bits<4> cond;
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bit annul = 0; // currently unused
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let cond = condVal;
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let op2 = op2Val;
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@ -53,7 +61,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
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// Format #3 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F3 : InstV8 {
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class F3<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern> {
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bits<5> rd;
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bits<6> op3;
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bits<5> rs1;
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@ -66,14 +75,10 @@ class F3 : InstV8 {
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<8> asi = 0; // asi not currently used in SparcV8
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bits<5> rs2;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -83,13 +88,9 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<13> simm13;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -99,13 +100,9 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
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// floating-point
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class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<5> rs2;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -15,19 +15,6 @@
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstV8 : Instruction { // SparcV8 instruction baseline
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to SparcV8 instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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@ -101,11 +88,9 @@ def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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class Pseudo<dag ops, string asmstr, list<dag> pattern> : InstV8 {
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let AsmString = asmstr;
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dag OperandList = ops;
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let Pattern = pattern;
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}
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class Pseudo<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern>;
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def PHI : Pseudo<(ops variable_ops), "PHI", []>;
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def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
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@ -542,12 +527,10 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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// pc-relative call:
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let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def CALL : InstV8 {
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let OperandList = (ops IntRegs:$dst);
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def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let AsmString = "call $dst";
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}
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// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
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@ -7,11 +7,26 @@
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//
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//===----------------------------------------------------------------------===//
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class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F2 : InstV8 { // Format 2 instructions
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// Format 2 instructions
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class F2<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern> {
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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@ -21,27 +36,20 @@ class F2 : InstV8 { // Format 2 instructions
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
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class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
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: F2<ops, asmstr, pattern> {
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bits<5> rd;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op2 = op2Val;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
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list<dag> pattern> : F2 {
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list<dag> pattern> : F2<ops, asmstr, pattern> {
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bits<4> cond;
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bit annul = 0; // currently unused
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let cond = condVal;
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let op2 = op2Val;
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@ -53,7 +61,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
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// Format #3 instruction classes in the SparcV8
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//===----------------------------------------------------------------------===//
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class F3 : InstV8 {
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class F3<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern> {
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bits<5> rd;
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bits<6> op3;
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bits<5> rs1;
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@ -66,14 +75,10 @@ class F3 : InstV8 {
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<8> asi = 0; // asi not currently used in SparcV8
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bits<5> rs2;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -83,13 +88,9 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<13> simm13;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -99,13 +100,9 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
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// floating-point
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class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
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bits<5> rs2;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -15,19 +15,6 @@
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstV8 : Instruction { // SparcV8 instruction baseline
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to SparcV8 instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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@ -101,11 +88,9 @@ def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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class Pseudo<dag ops, string asmstr, list<dag> pattern> : InstV8 {
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let AsmString = asmstr;
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dag OperandList = ops;
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let Pattern = pattern;
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}
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class Pseudo<dag ops, string asmstr, list<dag> pattern>
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: InstV8<ops, asmstr, pattern>;
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def PHI : Pseudo<(ops variable_ops), "PHI", []>;
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def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
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@ -542,12 +527,10 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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// pc-relative call:
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let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def CALL : InstV8 {
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let OperandList = (ops IntRegs:$dst);
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def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let AsmString = "call $dst";
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}
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// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
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