6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 22:24:07 +00:00
Code Issues Projects Releases Wiki Activity

- Change the horrible N^2 isRegReDefinedByTwoAddr. Now callers must supply the operand index of def machineoperand and at most one full scan of non-implicit operands is needed.

Browse Source 
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53394 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-07-10 07:35:43 +00:00
parent 5dcc41f5b3
commit ef0732d25a
5 changed files with 24 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
lib/CodeGen/MachineInstr.cpp
View File

@ -623,20 +623,15 @@ int MachineInstr::findFirstPredOperandIdx() const {
return -1;
}
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
/// check if the register def is a re-definition due to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
for (unsigned j = i+1; j < e; ++j) {
const MachineOperand &MO2 = getOperand(j);
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
return true;
}
}
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
return true;
}
return false;
}