Refactor isThumb1Only() && isMClass() into a predicate called isV6M()

This must be enforced for all v6M cores, not just the cortex-m0,
irregardless of the user-specified alignment.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219300 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2014-10-08 12:26:16 +00:00
parent 3828392790
commit ef2ed3f465
2 changed files with 8 additions and 5 deletions

View File

@ -310,15 +310,14 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
(hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
isTargetNetBSD())) ||
(hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
// The one exception is cortex-m0, which despite being v6, does not
// support unaligned accesses. Rather than make the above boolean
// expression even more obtuse, just override the value here.
if (isThumb1Only() && isMClass())
AllowsUnalignedMem = false;
} else {
AllowsUnalignedMem = !(Align == StrictAlign);
}
// No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
if (isV6M())
AllowsUnalignedMem = false;
switch (IT) {
case DefaultIT:
RestrictIT = hasV8Ops() ? true : false;

View File

@ -405,6 +405,10 @@ public:
bool isRClass() const { return ARMProcClass == RClass; }
bool isAClass() const { return ARMProcClass == AClass; }
bool isV6M() const {
return isThumb1Only() && isMClass();
}
bool isR9Reserved() const { return IsR9Reserved; }
bool useMovt(const MachineFunction &MF) const;