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Combine the two add with overflow intrinsics lowerings. They differ only in DAG node type.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-11-21 02:38:44 +00:00
parent f6b7a47d5d
commit ef37546f68
1 changed files with 5 additions and 18 deletions
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23
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -4093,8 +4093,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
}
case Intrinsic::uadd_with_overflow:
case Intrinsic::sadd_with_overflow: {
// Convert to "ISD::SADDO" instruction.
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
MVT Ty = Op1.getValueType();
@ -4102,23 +4102,10 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
MVT ValueVTs[] = { Ty, MVT::i1 };
SDValue Ops[] = { Op1, Op2 };
SDValue Result = DAG.getNode(ISD::SADDO, DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
setValue(&I, Result);
return 0;
}
case Intrinsic::uadd_with_overflow: {
// Convert to "ISD::UADDO" instruction.
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
MVT Ty = Op1.getValueType();
MVT ValueVTs[] = { Ty, MVT::i1 };
SDValue Ops[] = { Op1, Op2 };
SDValue Result = DAG.getNode(ISD::UADDO, DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
SDValue Result =
DAG.getNode((Intrinsic == Intrinsic::sadd_with_overflow) ?
ISD::SADDO : ISD::UADDO,
DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
setValue(&I, Result);
return 0;