From ef3c030e0e08b7d9446445823f4972fcf18c1ce1 Mon Sep 17 00:00:00 2001 From: Nicolas Geoffray Date: Tue, 3 Apr 2007 10:27:07 +0000 Subject: [PATCH] The ELF ABI specifies F1-F8 registers as argument registers for double, not F1-F10. This affects only ELF, not MachO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCCallingConv.td | 4 ++-- lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- lib/Target/PowerPC/PPCInstr64Bit.td | 2 +- lib/Target/PowerPC/PPCInstrInfo.td | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 8 +++++--- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 2b69d46bab6..b75ec40f6f4 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -44,8 +44,8 @@ def CC_PPC : CallingConv<[ // Darwin passes FP values in F1 - F13 CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()", CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>, - // Other sub-targets pass FP values in F1-10. - CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9,F10]>>, + // Other sub-targets pass FP values in F1-F8. + CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, // The first 12 Vector arguments are passed in altivec registers. CCIfType<[v16i8, v8i16, v4i32, v4f32], diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 4b29bc78862..5ac87104f99 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1113,7 +1113,7 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { static const unsigned FPR[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, - PPC::F8, PPC::F9, PPC::F10 + PPC::F8 }; return FPR; } @@ -1154,7 +1154,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, }; const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]); - const unsigned Num_FPR_Regs = isMachoABI ? 13 : 10; + const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]); unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; @@ -1410,7 +1410,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 }; const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); - const unsigned NumFPRs = isMachoABI ? 13 : 10; + const unsigned NumFPRs = isMachoABI ? 13 : 8; const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 56070b2b3f6..e6ede49fbee 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -91,7 +91,7 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, let isCall = 1, noResults = 1, PPC970_Unit = 7, // All calls clobber the PPC64 non-callee saved registers. Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, - F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, + F0,F1,F2,F3,F4,F5,F6,F7,F8, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR8,CTR8, CR0,CR1,CR5,CR6,CR7] in { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index cfdb3780acc..e43b33921b7 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -396,7 +396,7 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7, let isCall = 1, noResults = 1, PPC970_Unit = 7, // All calls clobber the non-callee saved registers... Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, - F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, + F0,F1,F2,F3,F4,F5,F6,F7,F8, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7] in { diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index a2ee9199462..6bd27160117 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -278,7 +278,8 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, - PPC::F11, PPC::F12, PPC::F13, + PPC::F9, + PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, @@ -320,8 +321,9 @@ const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, - - PPC::F11, PPC::F12, PPC::F13, + + PPC::F9, + PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25,