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TableGen no longer emit CopyFromReg nodes for implicit results in physical

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registers. The scheduler is now responsible for emitting them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-09-07 23:59:02 +00:00
parent 82d25148a7
commit ef61ed3507
3 changed files with 17 additions and 90 deletions
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44
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1063,50 +1063,6 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
break;
}
case ISD::MUL: {
if (NVT == MVT::i8) {
SDOperand N0 = Node->getOperand(0);
SDOperand N1 = Node->getOperand(1);
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
if (!foldedLoad) {
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
if (foldedLoad)
std::swap(N0, N1);
}
SDNode *ResNode;
if (foldedLoad) {
SDOperand Chain = N1.getOperand(0);
AddToISelQueue(N0);
AddToISelQueue(Chain);
AddToISelQueue(Tmp0);
AddToISelQueue(Tmp1);
AddToISelQueue(Tmp2);
AddToISelQueue(Tmp3);
SDOperand InFlag(0, 0);
Chain = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag);
InFlag = Chain.getValue(1);
SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
ResNode = CurDAG->getTargetNode(X86::MUL8m, MVT::i8, MVT::i8,
MVT::Other, Ops, 6);
ReplaceUses(N1.getValue(1), SDOperand(ResNode, 2));
} else {
SDOperand Chain = CurDAG->getEntryNode();
AddToISelQueue(N0);
AddToISelQueue(N1);
SDOperand InFlag(0, 0);
InFlag = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag).getValue(1);
ResNode = CurDAG->getTargetNode(X86::MUL8r, MVT::i8, MVT::i8,
N1, InFlag);
}
ReplaceUses(N.getValue(0), SDOperand(ResNode, 0));
return NULL;
}
break;
}
case ISD::MULHU:
case ISD::MULHS: {
if (Opcode == ISD::MULHU)

4
lib/Target/X86/X86InstrInfo.td
View File

@ -552,7 +552,7 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
[]>,
[(set AL, (mul AL, GR8:$src))]>,
Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
@ -563,7 +563,7 @@ def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
// FIXME: Used for 8-bit mul, ignore result upper 8 bits.
// This probably ought to be moved to a def : Pat<> if the
// syntax can be accepted.
[]>,
[(set AL, (mul AL, (loadi8 addr:$src)))]>,
Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
"mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,

59
utils/TableGen/DAGISelEmitter.cpp
View File

@ -2768,8 +2768,8 @@ public:
PatternHasProperty(Pattern, SDNPOptInFlag, ISE);
bool NodeHasInFlag = isRoot &&
PatternHasProperty(Pattern, SDNPInFlag, ISE);
bool NodeHasOutFlag = HasImpResults || (isRoot &&
PatternHasProperty(Pattern, SDNPOutFlag, ISE));
bool NodeHasOutFlag = isRoot &&
PatternHasProperty(Pattern, SDNPOutFlag, ISE);
bool NodeHasChain = InstPatNode &&
PatternHasProperty(InstPatNode, SDNPHasChain, ISE);
bool InputHasChain = isRoot &&
@ -2869,7 +2869,7 @@ public:
unsigned ResNo = TmpNo++;
if (!isRoot || InputHasChain || NodeHasChain || NodeHasOutFlag ||
NodeHasOptInFlag) {
NodeHasOptInFlag || HasImpResults) {
std::string Code;
std::string Code2;
std::string NodeName;
@ -2895,6 +2895,18 @@ public:
Code += ", VT" + utostr(VTNo);
emitVT(getEnumName(N->getTypeNum(0)));
}
// Add types for implicit results in physical registers, scheduler will
// care of adding copyfromreg nodes.
if (HasImpResults) {
for (unsigned i = 0, e = Inst.getNumImpResults(); i < e; i++) {
Record *RR = Inst.getImpResult(i);
if (RR->isSubClassOf("Register")) {
MVT::ValueType RVT = getRegisterValueType(RR, CGT);
Code += ", " + getEnumName(RVT);
++NumResults;
}
}
}
if (NodeHasChain)
Code += ", MVT::Other";
if (NodeHasOutFlag)
@ -2999,11 +3011,6 @@ public:
utostr(NumResults + (unsigned)NodeHasChain) + ");");
}
if (HasImpResults && EmitCopyFromRegs(N, ResNodeDecled, ChainEmitted)) {
emitCode("ReplaceUses(SDOperand(N.Val, 0), SDOperand(ResNode, 0));");
NumResults = 1;
}
if (FoldedChains.size() > 0) {
std::string Code;
for (unsigned j = 0, e = FoldedChains.size(); j < e; j++)
@ -3202,42 +3209,6 @@ private:
emitCode("AddToISelQueue(InFlag);");
}
}
/// EmitCopyFromRegs - Emit code to copy result to physical registers
/// as specified by the instruction. It returns true if any copy is
/// emitted.
bool EmitCopyFromRegs(TreePatternNode *N, bool &ResNodeDecled,
bool &ChainEmitted) {
bool RetVal = false;
Record *Op = N->getOperator();
if (Op->isSubClassOf("Instruction")) {
const DAGInstruction &Inst = ISE.getInstruction(Op);
const CodeGenTarget &CGT = ISE.getTargetInfo();
unsigned NumImpResults = Inst.getNumImpResults();
for (unsigned i = 0; i < NumImpResults; i++) {
Record *RR = Inst.getImpResult(i);
if (RR->isSubClassOf("Register")) {
MVT::ValueType RVT = getRegisterValueType(RR, CGT);
if (RVT != MVT::Flag) {
if (!ChainEmitted) {
emitCode("SDOperand Chain = CurDAG->getEntryNode();");
ChainEmitted = true;
ChainName = "Chain";
}
std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
emitCode(Decl + "ResNode = CurDAG->getCopyFromReg(" + ChainName +
", " + ISE.getQualifiedName(RR) + ", " + getEnumName(RVT) +
", InFlag).Val;");
ResNodeDecled = true;
emitCode(ChainName + " = SDOperand(ResNode, 1);");
emitCode("InFlag = SDOperand(ResNode, 2);");
RetVal = true;
}
}
}
}
return RetVal;
}
};
/// EmitCodeForPattern - Given a pattern to match, emit code to the specified