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Be more careful about order of arg evalution for CopyToReg nodes. This shrinks

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256.bzip2 from 7142 to 7103 lines of .s file.

Second, add initial support for folding loads into compares, though this code
is dynamically dead for now. :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19493 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-12 02:02:48 +00:00
parent 7ea64f5d12
commit ef6806c979
1 changed files with 47 additions and 2 deletions
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49
lib/Target/X86/X86ISelPattern.cpp
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@ -857,6 +857,22 @@ void ISel::EmitCMP(SDOperand LHS, SDOperand RHS) {
unsigned Opc;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS)) {
Opc = 0;
if (isFoldableLoad(LHS)) {
switch (RHS.getValueType()) {
default: break;
case MVT::i1:
case MVT::i8: Opc = X86::CMP8mi; break;
case MVT::i16: Opc = X86::CMP16mi; break;
case MVT::i32: Opc = X86::CMP32mi; break;
}
if (Opc) {
X86AddressMode AM;
EmitFoldedLoad(LHS, AM);
addFullAddress(BuildMI(BB, Opc, 5), AM).addImm(CN->getValue());
return;
}
}
switch (RHS.getValueType()) {
default: break;
case MVT::i1:
@ -871,6 +887,30 @@ void ISel::EmitCMP(SDOperand LHS, SDOperand RHS) {
}
}
Opc = 0;
if (isFoldableLoad(LHS)) {
switch (RHS.getValueType()) {
default: break;
case MVT::i1:
case MVT::i8: Opc = X86::CMP8mr; break;
case MVT::i16: Opc = X86::CMP16mr; break;
case MVT::i32: Opc = X86::CMP32mr; break;
}
if (Opc) {
X86AddressMode AM;
unsigned Reg;
if (getRegPressure(LHS) > getRegPressure(RHS)) {
EmitFoldedLoad(LHS, AM);
Reg = SelectExpr(RHS);
} else {
Reg = SelectExpr(RHS);
EmitFoldedLoad(LHS, AM);
}
addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(Reg);
return;
}
}
switch (LHS.getValueType()) {
default: assert(0 && "Cannot compare this value!");
case MVT::i1:
@ -1986,8 +2026,13 @@ void ISel::Select(SDOperand N) {
assert(0 && "Node not handled yet!");
case ISD::EntryToken: return; // Noop
case ISD::CopyToReg:
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
if (getRegPressure(N.getOperand(0)) > getRegPressure(N.getOperand(1))) {
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
} else {
Tmp1 = SelectExpr(N.getOperand(1));
Select(N.getOperand(0));
}
Tmp2 = cast<CopyRegSDNode>(N)->getReg();
if (Tmp1 != Tmp2) {