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Add the necessary support to codegen condition register logical ops with

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register allocated condition registers.  Make sure that the printed
  output is gas compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2005-04-14 03:20:38 +00:00
parent 1b7f7fbf95
commit ef7288c824
4 changed files with 72 additions and 17 deletions
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18
lib/Target/PowerPC/PPCInstrFormats.td
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@@ -309,8 +309,22 @@ class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
// 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr>
: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<3> CRD;
bits<2> CRDb;
bits<3> CRA;
bits<2> CRAb;
bits<3> CRB;
bits<2> CRBb;
let Inst{6-8} = CRD;
let Inst{9-10} = CRDb;
let Inst{11-13} = CRA;
let Inst{14-15} = CRAb;
let Inst{16-18} = CRB;
let Inst{19-20} = CRBb;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,