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Add support for the 'Q' constraint.

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Fixes rdar://9866494


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-07-29 21:18:58 +00:00
parent b4f4cbd199
commit ef7f1e71f7
2 changed files with 15 additions and 0 deletions
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3
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -7596,6 +7596,9 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
case 'x': return C_RegisterClass; case 'x': return C_RegisterClass;
case 't': return C_RegisterClass; case 't': return C_RegisterClass;
case 'j': return C_Other; // Constant for movw. case 'j': return C_Other; // Constant for movw.
// An address with a single base register. Due to the way we
// currently handle addresses it is the same as an 'r' memory constraint.
case 'Q': return C_Memory;
} }
} else if (Constraint.size() == 2) { } else if (Constraint.size() == 2) {
switch (Constraint[0]) { switch (Constraint[0]) {

12
test/CodeGen/ARM/inlineasm3.ll
View File

@ -98,3 +98,15 @@ entry:
%0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
ret i32 %0 ret i32 %0
} }
; Radar 9866494
define void @t10(i8* %f, i32 %g) nounwind {
entry:
; CHECK: t10
; CHECK: str r1, [r0]
%f.addr = alloca i8*, align 4
store i8* %f, i8** %f.addr, align 4
call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
ret void
}