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Thumb2 parsing and encoding for CMN and CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
c103a08a11
commit
ef88a92677
@ -798,7 +798,7 @@ multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
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ty:$imm, pred:$p,
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cc_out:$s)>;
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
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(!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
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rGPR:$Rm, pred:$p,
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@ -818,15 +818,15 @@ multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
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/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
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/// patterns. Similar to T2I_bin_irs except the instruction does not produce
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/// a explicit result, only implicitly set CPSR.
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let isCompare = 1, Defs = [CPSR] in {
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multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode> {
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PatFrag opnode, string baseOpc> {
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let isCompare = 1, Defs = [CPSR] in {
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// shifted imm
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def ri : T2OneRegCmpImm<
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(outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
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(outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
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opc, ".w\t$Rn, $imm",
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[(opnode GPR:$Rn, t2_so_imm:$imm)]> {
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[(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -836,9 +836,9 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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}
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// register
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def rr : T2TwoRegCmp<
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(outs), (ins GPR:$Rn, rGPR:$Rm), iir,
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(outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
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opc, ".w\t$Rn, $Rm",
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[(opnode GPR:$Rn, rGPR:$Rm)]> {
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[(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -850,9 +850,9 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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}
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// shifted register
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def rs : T2OneRegCmpShiftedReg<
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(outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
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(outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
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opc, ".w\t$Rn, $ShiftedRm",
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[(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
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[(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -860,6 +860,17 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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let Inst{11-8} = 0b1111; // Rd
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}
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}
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// Assembler aliases w/o the ".w" suffix.
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// No alias here for 'rr' version as not all instantiations of this
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// multiclass want one (CMP in particular, does not).
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def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
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t2_so_imm:$imm, pred:$p)>;
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def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
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(!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
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t2_so_reg:$shift,
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pred:$p)>;
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}
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/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
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@ -2646,14 +2657,14 @@ def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
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//
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defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
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IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
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BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
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BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
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def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
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(t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
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def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
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(t2CMPrr GPR:$lhs, rGPR:$rhs)>;
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def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
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(t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
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def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
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(t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
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def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
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(t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
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def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
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(t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
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//FIXME: Disable CMN, as CCodes are backwards from compare expectations
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// Compare-to-zero still works out, just not the relationals
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@ -2661,20 +2672,23 @@ def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
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// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
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defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
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IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
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BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
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BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
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"t2CMNz">;
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//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
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// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
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def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
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(t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
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def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
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(t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
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defm t2TST : T2I_cmp_irs<0b0000, "tst",
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
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BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
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BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
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"t2TST">;
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defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
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BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
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BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
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"t2TEQ">;
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// Conditional moves
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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@ -3567,3 +3581,12 @@ def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
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(t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
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pred:$p, cc_out:$s)>;
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// Alias for compares without the ".w" optional width specifier.
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def : t2InstAlias<"cmn${p} $Rn, $Rm",
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(t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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def : t2InstAlias<"teq${p} $Rn, $Rm",
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(t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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def : t2InstAlias<"tst${p} $Rn, $Rm",
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(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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@ -316,6 +316,46 @@ _func:
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@ CHECK: clzeq r1, r2 @ encoding: [0xb2,0xfa,0x82,0xf1]
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@------------------------------------------------------------------------------
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@ CMN
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@------------------------------------------------------------------------------
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cmn r1, #0xf
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cmn r8, r6
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cmn r1, r6, lsl #10
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cmn r1, r6, lsr #10
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cmn sp, r6, lsr #10
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cmn r1, r6, asr #10
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cmn r1, r6, ror #10
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@ CHECK: cmn.w r1, #15 @ encoding: [0x11,0xf1,0x0f,0x0f]
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@ CHECK: cmn.w r8, r6 @ encoding: [0x18,0xeb,0x06,0x0f]
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@ CHECK: cmn.w r1, r6, lsl #10 @ encoding: [0x11,0xeb,0x86,0x2f]
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@ CHECK: cmn.w r1, r6, lsr #10 @ encoding: [0x11,0xeb,0x96,0x2f]
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@ CHECK: cmn.w sp, r6, lsr #10 @ encoding: [0x1d,0xeb,0x96,0x2f]
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@ CHECK: cmn.w r1, r6, asr #10 @ encoding: [0x11,0xeb,0xa6,0x2f]
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@ CHECK: cmn.w r1, r6, ror #10 @ encoding: [0x11,0xeb,0xb6,0x2f]
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@------------------------------------------------------------------------------
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@ CMP
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@------------------------------------------------------------------------------
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cmp r5, #0xff00
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cmp.w r4, r12
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cmp r9, r6, lsl #12
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cmp r3, r7, lsr #31
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cmp sp, r6, lsr #1
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cmp r2, r5, asr #24
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cmp r1, r4, ror #15
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@ CHECK: cmp.w r5, #65280 @ encoding: [0xb5,0xf5,0x7f,0x4f]
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@ CHECK: cmp.w r4, r12 @ encoding: [0xb4,0xeb,0x0c,0x0f]
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@ CHECK: cmp.w r9, r6, lsl #12 @ encoding: [0xb9,0xeb,0x06,0x3f]
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@ CHECK: cmp.w r3, r7, lsr #31 @ encoding: [0xb3,0xeb,0xd7,0x7f]
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@ CHECK: cmp.w sp, r6, lsr #1 @ encoding: [0xbd,0xeb,0x56,0x0f]
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@ CHECK: cmp.w r2, r5, asr #24 @ encoding: [0xb2,0xeb,0x25,0x6f]
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@ CHECK: cmp.w r1, r4, ror #15 @ encoding: [0xb1,0xeb,0xf4,0x3f]
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@------------------------------------------------------------------------------
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@ IT
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@------------------------------------------------------------------------------
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