diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index c103dd6f374..78186cfc784 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -77,13 +77,16 @@ def TBU : SPR<5>;
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : 
   RegisterClass<i32, 4, 
-    [R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, 
+    [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, 
      R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-     R16, R15, R14, R13, R0, R2, R1, LR]>
+     R16, R15, R14, R13, R0, R1, LR]>
 {
   let Methods = [{
+    iterator allocation_order_begin(MachineFunction &MF) const {
+      return begin() + (AIX ? 1 : 0);
+    }
     iterator allocation_order_end(MachineFunction &MF) const {
-      return end() - (AIX ? 4 : 3);
+      return end() - 3;
     }
   }];
 }