6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-18 12:29:21 +00:00
Code Issues Projects Releases Wiki Activity

Correct returns of 64-bit values, though they seemed to work before...

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28892 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-06-21 00:34:03 +00:00
parent 76f6115424
commit ef95710583
1 changed files with 19 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -733,8 +733,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
Op.getOperand(1), Op.getOperand(2)); Op.getOperand(1), Op.getOperand(2));
} }
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, static SDOperand LowerFORMAL_ARGUMENTS_32(SDOperand Op, SelectionDAG &DAG,
int &VarArgsFrameIndex) { int &VarArgsFrameIndex) {
// TODO: add description of PPC stack frame format, or at least some docs. // TODO: add description of PPC stack frame format, or at least some docs.
// //
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
@ -883,6 +883,11 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues); return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
} }
static SDOperand LowerFORMAL_ARGUMENTS_64(SDOperand Op, SelectionDAG &DAG,
int &VarArgsFrameIndex) {
return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
}
/// isCallCompatibleAddress - Return the immediate to use if the specified /// isCallCompatibleAddress - Return the immediate to use if the specified
/// 32-bit value is representable in the immediate field of a BxA instruction. /// 32-bit value is representable in the immediate field of a BxA instruction.
static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
@ -1165,13 +1170,15 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
case 3: { case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg; unsigned ArgReg;
if (MVT::isVector(ArgVT)) if (ArgVT == MVT::i32) {
ArgReg = PPC::V2;
else if (MVT::isInteger(ArgVT))
ArgReg = PPC::R3; ArgReg = PPC::R3;
else { } else if (ArgVT == MVT::i64) {
assert(MVT::isFloatingPoint(ArgVT)); ArgReg = PPC::X3;
} else if (MVT::isFloatingPoint(ArgVT)) {
ArgReg = PPC::F1; ArgReg = PPC::F1;
} else {
assert(MVT::isVector(ArgVT));
ArgReg = PPC::V2;
} }
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
@ -2128,8 +2135,11 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::JumpTable: return LowerJumpTable(Op, DAG); case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, case ISD::FORMAL_ARGUMENTS:
VarArgsFrameIndex); if (getPointerTy() == MVT::i32)
return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
else
return LowerFORMAL_ARGUMENTS_64(Op, DAG, VarArgsFrameIndex);
case ISD::CALL: return LowerCALL(Op, DAG); case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET: return LowerRET(Op, DAG); case ISD::RET: return LowerRET(Op, DAG);