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https://github.com/c64scene-ar/llvm-6502.git
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Correct returns of 64-bit values, though they seemed to work before...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28892 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -733,8 +733,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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Op.getOperand(1), Op.getOperand(2));
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Op.getOperand(1), Op.getOperand(2));
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}
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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static SDOperand LowerFORMAL_ARGUMENTS_32(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsFrameIndex) {
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int &VarArgsFrameIndex) {
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// TODO: add description of PPC stack frame format, or at least some docs.
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// TODO: add description of PPC stack frame format, or at least some docs.
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//
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFunction &MF = DAG.getMachineFunction();
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@ -883,6 +883,11 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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}
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}
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static SDOperand LowerFORMAL_ARGUMENTS_64(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsFrameIndex) {
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return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
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}
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/// isCallCompatibleAddress - Return the immediate to use if the specified
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/// isCallCompatibleAddress - Return the immediate to use if the specified
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/// 32-bit value is representable in the immediate field of a BxA instruction.
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/// 32-bit value is representable in the immediate field of a BxA instruction.
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static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
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static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
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@ -1165,13 +1170,15 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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case 3: {
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case 3: {
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MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
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MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
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unsigned ArgReg;
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unsigned ArgReg;
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if (MVT::isVector(ArgVT))
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if (ArgVT == MVT::i32) {
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ArgReg = PPC::V2;
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else if (MVT::isInteger(ArgVT))
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ArgReg = PPC::R3;
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ArgReg = PPC::R3;
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else {
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} else if (ArgVT == MVT::i64) {
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assert(MVT::isFloatingPoint(ArgVT));
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ArgReg = PPC::X3;
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} else if (MVT::isFloatingPoint(ArgVT)) {
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ArgReg = PPC::F1;
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ArgReg = PPC::F1;
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} else {
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assert(MVT::isVector(ArgVT));
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ArgReg = PPC::V2;
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}
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}
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Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
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Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
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@ -2128,8 +2135,11 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
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case ISD::FORMAL_ARGUMENTS:
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VarArgsFrameIndex);
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if (getPointerTy() == MVT::i32)
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return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
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else
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return LowerFORMAL_ARGUMENTS_64(Op, DAG, VarArgsFrameIndex);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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