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Cleanup whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158443 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -177,7 +177,6 @@ class ARMFastISel : public FastISel {
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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unsigned Alignment = 0, bool isZExt = true,
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unsigned Alignment = 0, bool isZExt = true,
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bool allocReg = true);
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bool allocReg = true);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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unsigned Alignment = 0);
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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@ -1356,7 +1355,7 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
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unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
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unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
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.addReg(AddrReg));
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.addReg(AddrReg));
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return true;
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return true;
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}
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}
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bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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@ -1735,7 +1734,7 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
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// type and the target independent selector doesn't know how to handle it.
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// type and the target independent selector doesn't know how to handle it.
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if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
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if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
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return false;
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return false;
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unsigned Opc;
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unsigned Opc;
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switch (ISDOpcode) {
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switch (ISDOpcode) {
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default: return false;
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default: return false;
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@ -2141,7 +2140,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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return false;
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return false;
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// Can't handle non-double multi-reg retvals.
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// Can't handle non-double multi-reg retvals.
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if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
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if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
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SmallVector<CCValAssign, 16> RVLocs;
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
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CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
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CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
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CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
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@ -2347,7 +2346,7 @@ bool ARMFastISel::SelectCall(const Instruction *I,
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MIB.addReg(CalleeReg);
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MIB.addReg(CalleeReg);
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else if (!IntrMemName)
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else if (!IntrMemName)
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MIB.addGlobalAddress(GV, 0, 0);
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MIB.addGlobalAddress(GV, 0, 0);
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else
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else
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MIB.addExternalSymbol(IntrMemName, 0);
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MIB.addExternalSymbol(IntrMemName, 0);
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} else {
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} else {
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if (UseReg)
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if (UseReg)
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@ -2360,7 +2359,7 @@ bool ARMFastISel::SelectCall(const Instruction *I,
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// Explicitly adding the predicate here.
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// Explicitly adding the predicate here.
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AddDefaultPred(MIB);
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AddDefaultPred(MIB);
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}
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}
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// Add implicit physical register uses to the call.
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// Add implicit physical register uses to the call.
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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MIB.addReg(RegArgs[i]);
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MIB.addReg(RegArgs[i]);
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@ -2481,10 +2480,10 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
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return true;
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return true;
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}
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}
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}
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}
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if (!MTI.getLength()->getType()->isIntegerTy(32))
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if (!MTI.getLength()->getType()->isIntegerTy(32))
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return false;
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return false;
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if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
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if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
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return false;
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return false;
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@ -2496,13 +2495,13 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
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// Don't handle volatile.
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// Don't handle volatile.
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if (MSI.isVolatile())
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if (MSI.isVolatile())
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return false;
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return false;
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if (!MSI.getLength()->getType()->isIntegerTy(32))
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if (!MSI.getLength()->getType()->isIntegerTy(32))
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return false;
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return false;
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if (MSI.getDestAddressSpace() > 255)
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if (MSI.getDestAddressSpace() > 255)
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return false;
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return false;
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return SelectCall(&I, "memset");
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return SelectCall(&I, "memset");
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}
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}
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case Intrinsic::trap: {
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case Intrinsic::trap: {
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@ -2513,7 +2512,7 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
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}
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}
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bool ARMFastISel::SelectTrunc(const Instruction *I) {
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bool ARMFastISel::SelectTrunc(const Instruction *I) {
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// The high bits for a type smaller than the register size are assumed to be
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// The high bits for a type smaller than the register size are assumed to be
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// undefined.
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// undefined.
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Value *Op = I->getOperand(0);
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Value *Op = I->getOperand(0);
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@ -2704,7 +2703,7 @@ bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
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// See if we can handle this address.
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// See if we can handle this address.
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Address Addr;
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Address Addr;
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if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
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if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
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unsigned ResultReg = MI->getOperand(0).getReg();
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unsigned ResultReg = MI->getOperand(0).getReg();
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if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
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if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
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return false;
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return false;
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