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Add some asserts to catch copyRegToReg() fails early
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84983 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -195,7 +195,9 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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// Insert sub-register copy
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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(void)Emitted;
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assert(Emitted && "Subreg and Dst must be of compatible register class");
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// Transfer the kill/dead flags, if needed.
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// Transfer the kill/dead flags, if needed.
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if (MI->getOperand(0).isDead())
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if (MI->getOperand(0).isDead())
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TransferDeadFlag(MI, DstSubReg, TRI);
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TransferDeadFlag(MI, DstSubReg, TRI);
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@ -264,8 +266,11 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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// KILL.
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// KILL.
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII.get(TargetInstrInfo::KILL), DstSubReg);
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TII.get(TargetInstrInfo::KILL), DstSubReg);
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else
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else {
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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(void)Emitted;
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assert(Emitted && "Subreg and Dst must be of compatible register class");
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}
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MachineBasicBlock::iterator CopyMI = MI;
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MachineBasicBlock::iterator CopyMI = MI;
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--CopyMI;
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--CopyMI;
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