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add a simple dag combine to replace trivial shl+lshr with

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and.  This happens with the store->load narrowing stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-04-15 05:28:43 +00:00
parent 2392ae7d73
commit efcddc3325
2 changed files with 10 additions and 1 deletions
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9
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2735,6 +2735,15 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(c1 + c2, N1.getValueType())); DAG.getConstant(c1 + c2, N1.getValueType()));
} }
// fold (srl (shl x, c), c) -> (and x, cst2)
if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
N0.getValueSizeInBits() <= 64) {
uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
DAG.getConstant(~0ULL >> ShAmt, VT));
}
// fold (srl (anyextend x), c) -> (anyextend (srl x, c)) // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {

2
test/CodeGen/ARM/sbfx.ll
View File

@ -12,7 +12,7 @@ entry:
define i32 @f2(i32 %a) { define i32 @f2(i32 %a) {
entry: entry:
; CHECK: f2: ; CHECK: f2:
; CHECK: ubfx r0, r0, #0, #20 ; CHECK: bfc r0, #20, #12
%tmp = shl i32 %a, 12 %tmp = shl i32 %a, 12
%tmp2 = lshr i32 %tmp, 12 %tmp2 = lshr i32 %tmp, 12
ret i32 %tmp2 ret i32 %tmp2