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https://github.com/c64scene-ar/llvm-6502.git
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Add more comments to the ASM output for the CIE's "moves".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134194 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -565,6 +565,7 @@ static void EmitEncodingByte(MCStreamer &Streamer, unsigned Encoding,
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void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
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const MCCFIInstruction &Instr) {
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int dataAlignmentFactor = getDataAlignmentFactor(Streamer);
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bool VerboseAsm = Streamer.isVerboseAsm();
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switch (Instr.getOperation()) {
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case MCCFIInstruction::Move:
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@ -576,9 +577,13 @@ void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
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// If advancing cfa.
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if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
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if (Src.getReg() == MachineLocation::VirtualFP) {
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if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa_offset");
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Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_offset, 1);
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} else {
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if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa");
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Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Reg ") +
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Twine(Src.getReg()));
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Streamer.EmitULEB128IntValue(Src.getReg());
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}
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@ -587,47 +592,61 @@ void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
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else
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CFAOffset = -Src.getOffset();
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if (VerboseAsm) Streamer.AddComment(Twine("Offset " + Twine(CFAOffset)));
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Streamer.EmitULEB128IntValue(CFAOffset);
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return;
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}
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if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
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assert(Dst.isReg() && "Machine move not supported yet.");
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if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa_register");
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Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_register, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Dst.getReg()));
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Streamer.EmitULEB128IntValue(Dst.getReg());
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return;
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}
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unsigned Reg = Src.getReg();
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int Offset = Dst.getOffset();
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if (IsRelative)
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Offset -= CFAOffset;
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Offset = Offset / dataAlignmentFactor;
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if (Offset < 0) {
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if (VerboseAsm) Streamer.AddComment("DW_CFA_offset_extended_sf");
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Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended_sf, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
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Streamer.EmitULEB128IntValue(Reg);
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if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
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Streamer.EmitSLEB128IntValue(Offset);
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} else if (Reg < 64) {
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if (VerboseAsm) Streamer.AddComment("DW_CFA_offset");
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Streamer.EmitIntValue(dwarf::DW_CFA_offset + Reg, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
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Streamer.EmitULEB128IntValue(Offset);
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} else {
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if (VerboseAsm) Streamer.AddComment("DW_CFA_offset_extended");
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Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
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Streamer.EmitULEB128IntValue(Reg);
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if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
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Streamer.EmitULEB128IntValue(Offset);
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}
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return;
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}
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case MCCFIInstruction::Remember:
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if (VerboseAsm) Streamer.AddComment("DW_CFA_remember_state");
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Streamer.EmitIntValue(dwarf::DW_CFA_remember_state, 1);
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return;
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case MCCFIInstruction::Restore:
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if (VerboseAsm) Streamer.AddComment("DW_CFA_restore_state");
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Streamer.EmitIntValue(dwarf::DW_CFA_restore_state, 1);
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return;
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case MCCFIInstruction::SameValue: {
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unsigned Reg = Instr.getDestination().getReg();
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if (VerboseAsm) Streamer.AddComment("DW_CFA_same_value");
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Streamer.EmitIntValue(dwarf::DW_CFA_same_value, 1);
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if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
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Streamer.EmitULEB128IntValue(Reg);
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return;
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}
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