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Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
ce88835110
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efdd4673d6
@ -63,6 +63,8 @@ def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
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"Enable the popcnt[dw] instructions">;
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def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
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"Enable the ldbrx instruction">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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@ -77,7 +79,6 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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// FPRND p5x, p6, p6x, p7 frim, frin, frip, friz
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// FRE p5 through p7 fre (vs. fres, available since p3)
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// FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)
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// LDBRX p7 load with byte reversal
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// LFIWAX p6, p6x, p7 lfiwax
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// LFIWZX p7 lfiwzx
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// POPCNTB p5 through p7 popcntb and related instructions
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@ -129,17 +130,16 @@ def : ProcessorModel<"e500mc", PPCE500mcModel,
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def : ProcessorModel<"e5500", PPCE5500Model,
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[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
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FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
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def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */,
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FeatureQPX]>;
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def : Processor<"a2", PPCA2Itineraries,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"a2q", PPCA2Itineraries,
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[DirectiveA2, FeatureBookE, FeatureMFOCRF,
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FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
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FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
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/*, Feature64BitRegs */, FeatureQPX]>;
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def : Processor<"pwr3", G5Itineraries,
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[DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
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FeatureSTFIWX, Feature64Bit]>;
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@ -162,8 +162,8 @@ def : Processor<"pwr6x", G5Itineraries,
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def : Processor<"pwr7", G5Itineraries,
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[DirectivePwr7, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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FeatureISEL, FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */]>;
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FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : Processor<"ppc64", G5Itineraries,
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[Directive64, FeatureAltivec,
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@ -6604,7 +6604,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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N->getOperand(1).getOpcode() == ISD::BSWAP &&
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N->getOperand(1).getNode()->hasOneUse() &&
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(N->getOperand(1).getValueType() == MVT::i32 ||
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N->getOperand(1).getValueType() == MVT::i16)) {
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N->getOperand(1).getValueType() == MVT::i16 ||
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(TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
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N->getOperand(1).getValueType() == MVT::i64))) {
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SDValue BSwapOp = N->getOperand(1).getOperand(0);
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// Do an any-extend to 32-bits if this is a half-word input.
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if (BSwapOp.getValueType() == MVT::i16)
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@ -6625,7 +6627,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
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if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
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N->getOperand(0).hasOneUse() &&
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(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
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(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
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(TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
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N->getValueType(0) == MVT::i64))) {
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SDValue Load = N->getOperand(0);
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LoadSDNode *LD = cast<LoadSDNode>(Load);
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// Create the byte-swapping load.
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@ -6636,7 +6640,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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};
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SDValue BSLoad =
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DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
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DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
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DAG.getVTList(N->getValueType(0) == MVT::i64 ?
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MVT::i64 : MVT::i32, MVT::Other),
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Ops, 3,
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LD->getMemoryVT(), LD->getMemOperand());
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// If this is an i16 load, insert the truncate.
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@ -658,7 +658,10 @@ def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
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def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
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"ldx $rD, $src", LdStLD,
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[(set i64:$rD, (load xaddr:$src))]>, isPPC64;
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def LDBRX : XForm_1<31, 532, (outs G8RC:$rD), (ins memrr:$src),
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"ldbrx $rD, $src", LdStLoad,
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[(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
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let mayLoad = 1 in
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def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
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"ldu $rD, $addr", LdStLDU,
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@ -779,6 +782,11 @@ def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
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"stdx $rS, $dst", LdStSTD,
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[(store i64:$rS, xaddr:$dst)]>, isPPC64,
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PPC970_DGroup_Cracked;
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def STDBRX: XForm_8<31, 660, (outs), (ins G8RC:$rS, memrr:$dst),
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"stdbrx $rS, $dst", LdStStore,
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[(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
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PPC970_DGroup_Cracked;
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// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
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def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
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"std $rT, $dst", LdStSTD,
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@ -36,10 +36,10 @@ def SDT_PPCcondbr : SDTypeProfile<0, 3, [
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]>;
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def SDT_PPClbrx : SDTypeProfile<1, 2, [
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SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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]>;
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def SDT_PPCstbrx : SDTypeProfile<0, 3, [
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SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
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]>;
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def SDT_PPClarx : SDTypeProfile<1, 1, [
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@ -41,6 +41,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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, HasSTFIWX(false)
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, HasISEL(false)
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, HasPOPCNTD(false)
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, HasLDBRX(false)
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, IsBookE(false)
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, HasLazyResolverStubs(false)
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, IsJITCodeModel(false)
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@ -80,6 +80,7 @@ protected:
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bool HasSTFIWX;
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bool HasISEL;
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bool HasPOPCNTD;
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bool HasLDBRX;
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bool IsBookE;
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bool HasLazyResolverStubs;
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bool IsJITCodeModel;
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@ -161,6 +162,7 @@ public:
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasPOPCNTD() const { return HasPOPCNTD; }
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bool hasLDBRX() const { return HasLDBRX; }
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bool isBookE() const { return IsBookE; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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@ -1,5 +1,6 @@
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; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7
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define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
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@ -34,18 +35,47 @@ define i16 @LHBRX(i8* %ptr, i32 %off) {
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ret i16 %tmp6
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}
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define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
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%tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1]
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%tmp1.upgrd.1 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1]
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%tmp13 = tail call i64 @llvm.bswap.i64( i64 %i ) ; <i64> [#uses=1]
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store i64 %tmp13, i64* %tmp1.upgrd.1
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ret void
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}
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define i64 @LDBRX(i8* %ptr, i64 %off) {
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%tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1]
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%tmp1.upgrd.2 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1]
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%tmp = load i64* %tmp1.upgrd.2 ; <i64> [#uses=1]
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%tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp ) ; <i64> [#uses=1]
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ret i64 %tmp14
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}
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declare i32 @llvm.bswap.i32(i32)
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declare i16 @llvm.bswap.i16(i16)
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declare i64 @llvm.bswap.i64(i64)
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; X32: stwbrx
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; X32: lwbrx
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; X32: sthbrx
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; X32: lhbrx
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; X32-NOT: ldbrx
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; X32-NOT: stdbrx
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; X64: stwbrx
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; X64: lwbrx
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; X64: sthbrx
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; X64: lhbrx
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; X64-NOT: ldbrx
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; X64-NOT: stdbrx
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; PWR7: stwbrx
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; PWR7: lwbrx
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; PWR7: sthbrx
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; PWR7: lhbrx
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; PWR7: stdbrx
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; PWR7: ldbrx
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