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Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
to use AddrMode4, there was a count of the registers stored in one of the operands. I changed that to just count the operands but forgot to adjust for the size of D registers. This was noticed by Evan as a performance problem but it is a potential correctness bug as well, since it is possible that this could merge a base update with a non-matching immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113576 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -458,9 +458,10 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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case ARM::t2STM:
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case ARM::VLDMS:
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case ARM::VSTMS:
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return (MI->getNumOperands() - 4) * 4;
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case ARM::VLDMD:
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case ARM::VSTMD:
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return (MI->getNumOperands() - 4) * 4;
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return (MI->getNumOperands() - 4) * 8;
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}
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}
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@ -1,11 +1,15 @@
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; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
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; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
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@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
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@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
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@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
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; CHECK: dct_luma_sp:
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define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
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entry:
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; Make sure to use base-updating stores for saving callee-saved registers.
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; CHECK-NOT: sub sp
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; CHECK: vstmdb sp!
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%predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1]
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br label %cond_next489
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