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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-03 17:10:41 +00:00
parent 8b8e5a7f96
commit f033b5a393
1 changed files with 4 additions and 3 deletions
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7
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -380,9 +380,10 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset){
if (N.getOpcode() != ISD::ADD) {
Base = N;
// We must materialize a zero in a reg! Returning an constant here won't
// work since its node is -1 so it won't get added to the selection queue.
// Explicitly issue a tMOVri8 node!
// We must materialize a zero in a reg! Returning a constant here
// wouldn't work without additional code to position the node within
// ISel's topological ordering in a place where ISel will process it
// normally. Instead, just explicitly issue a tMOVri8 node!
Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
return true;