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Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-07-08 22:16:47 +00:00
parent abc43e69ea
commit f06ff4eae3
3 changed files with 2 additions and 38 deletions
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28
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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@ -35,7 +35,7 @@ using namespace llvm;
std::string X86_MC::ParseX86Triple(StringRef TT) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::x86_64)
return "+64bit-mode";
return "+64bit-mode,+64bit,+sse2";
return "-64bit-mode";
}
@ -107,28 +107,6 @@ void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
}
}
static bool hasX86_64() {
// FIXME: Code duplication. See X86Subtarget::AutoDetectSubtargetFeatures.
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
unsigned u[3];
char c[12];
} text;
if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return false;
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
if (IsIntel || IsAMD) {
X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 29) & 0x1)
return true;
}
return false;
}
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT);
@ -148,10 +126,6 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
#endif
}
if (ArchFS.empty() && CPUName.empty() && hasX86_64())
// Auto-detect if host is 64-bit capable, it's the default if true.
ArchFS = "+64bit-mode";
MCSubtargetInfo *X = new MCSubtargetInfo();
InitX86MCSubtargetInfo(X, CPUName, ArchFS);
return X;

10
lib/Target/X86/X86Subtarget.cpp
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@ -286,16 +286,6 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
if (In64BitMode && !HasAVX && X86SSELevel < SSE2)
X86SSELevel = SSE2;
}
// If requesting codegen for X86-64, make sure that 64-bit features
// are enabled.
// FIXME: Remove this feature since it's not actually being used.
if (In64BitMode) {
HasX86_64 = true;
// All 64-bit cpus have cmov support.
HasCMov = true;
}
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
<< ", 3DNowLevel " << X863DNowLevel

2
test/CodeGen/X86/sse1.ll
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@ -1,6 +1,6 @@
; Tests for SSE1 and below, without SSE2+.
; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=pentium3 -O3 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s
define <8 x i16> @test1(<8 x i32> %a) nounwind {
; CHECK: test1