diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 89457d7f45d..c9f26d117b8 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -145,8 +145,10 @@ def immSExt8 : PatLeaf<(imm), [{ //===----------------------------------------------------------------------===// // Instruction templates... -class I o, Format f, dag ops, string asm> - : X86Inst; +class I o, Format f, dag ops, string asm, list pattern> + : X86Inst { + let Pattern = pattern; +} class Ii8 o, Format f, dag ops, string asm, list pattern> : X86Inst { let Pattern = pattern; @@ -164,17 +166,17 @@ class Ii32 o, Format f, dag ops, string asm, list pattern> // Instruction list... // -def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">; // PHI node. -def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop +def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node. +def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop -def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN">; +def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>; def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), - "#ADJCALLSTACKUP">; -def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE">; -def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF">; + "#ADJCALLSTACKUP", []>; +def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; +def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">; + def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; //===----------------------------------------------------------------------===// // Control Flow Instructions... @@ -182,13 +184,14 @@ let isTerminator = 1 in // Return instructions. let isTerminator = 1, isReturn = 1, isBarrier = 1 in - def RET : I<0xC3, RawFrm, (ops), "ret">; + def RET : I<0xC3, RawFrm, (ops), "ret", []>; let isTerminator = 1, isReturn = 1, isBarrier = 1 in def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in - class IBr opcode, dag ops, string asm> : I; + class IBr opcode, dag ops, string asm> : + I; let isBarrier = 1 in def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">; @@ -215,18 +218,19 @@ let isCall = 1 in // All calls clobber the non-callee saved registers... let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { - def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">; - def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">; - def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">; + def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>; + def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>; + def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>; } // Tail call stuff. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in - def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL">; + def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in - def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst # TAIL CALL">; + def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), + "jmp {*}$dst # TAIL CALL", []>; // ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every // way, except that it is marked as being a terminator. This causes the epilog @@ -241,63 +245,63 @@ let isTerminator = 1, isTwoAddress = 1 in // Miscellaneous Instructions... // def LEAVE : I<0xC9, RawFrm, - (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>; + (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; def POP32r : I<0x58, AddRegFrm, - (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>; + (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; let isTwoAddress = 1 in // R32 = bswap R32 def BSWAP32r : I<0xC8, AddRegFrm, - (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB; + (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB; def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 (ops R8:$src1, R8:$src2), - "xchg{b} {$src2|$src1}, {$src1|$src2}">; + "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 (ops R16:$src1, R16:$src2), - "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; + "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 (ops R32:$src1, R32:$src2), - "xchg{l} {$src2|$src1}, {$src1|$src2}">; + "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8mr : I<0x86, MRMDestMem, (ops i8mem:$src1, R8:$src2), - "xchg{b} {$src2|$src1}, {$src1|$src2}">; + "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16mr : I<0x87, MRMDestMem, (ops i16mem:$src1, R16:$src2), - "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; + "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32mr : I<0x87, MRMDestMem, (ops i32mem:$src1, R32:$src2), - "xchg{l} {$src2|$src1}, {$src1|$src2}">; + "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8rm : I<0x86, MRMSrcMem, (ops R8:$src1, i8mem:$src2), - "xchg{b} {$src2|$src1}, {$src1|$src2}">; + "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16rm : I<0x87, MRMSrcMem, (ops R16:$src1, i16mem:$src2), - "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; + "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32rm : I<0x87, MRMSrcMem, (ops R32:$src1, i32mem:$src2), - "xchg{l} {$src2|$src1}, {$src1|$src2}">; + "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def LEA16r : I<0x8D, MRMSrcMem, (ops R16:$dst, i32mem:$src), - "lea{w} {$src|$dst}, {$dst|$src}">, OpSize; + "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; def LEA32r : I<0x8D, MRMSrcMem, (ops R32:$dst, i32mem:$src), - "lea{l} {$src|$dst}, {$dst|$src}">; + "lea{l} {$src|$dst}, {$dst|$src}", []>; -def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">, +def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">, +def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; -def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">, +def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">, +def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>, Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; -def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">, +def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>, Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; -def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">, +def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>, Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; @@ -305,11 +309,11 @@ def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">, // Input/Output Instructions... // def IN8rr : I<0xEC, RawFrm, (ops), - "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>; + "in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>; def IN16rr : I<0xED, RawFrm, (ops), - "in{w} {%dx, %ax|%AX, %DX}">, Imp<[DX], [AX]>, OpSize; + "in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize; def IN32rr : I<0xED, RawFrm, (ops), - "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>; + "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>; def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port), "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>; @@ -319,11 +323,11 @@ def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>; def OUT8rr : I<0xEE, RawFrm, (ops), - "out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>; + "out{b} {%al, %dx|%DX, %AL}", []>, Imp<[DX, AL], []>; def OUT16rr : I<0xEF, RawFrm, (ops), - "out{w} {%ax, %dx|%DX, %AX}">, Imp<[DX, AX], []>, OpSize; + "out{w} {%ax, %dx|%DX, %AX}", []>, Imp<[DX, AX], []>, OpSize; def OUT32rr : I<0xEF, RawFrm, (ops), - "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>; + "out{l} {%eax, %dx|%DX, %EAX}", []>, Imp<[DX, EAX], []>; def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port), "out{b} {%al, $port|$port, %AL}", []>, Imp<[AL], []>; @@ -336,11 +340,11 @@ def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), // Move Instructions... // def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), - "mov{b} {$src, $dst|$dst, $src}">; + "mov{b} {$src, $dst|$dst, $src}", []>; def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), - "mov{w} {$src, $dst|$dst, $src}">, OpSize; + "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), - "mov{l} {$src, $dst|$dst, $src}">; + "mov{l} {$src, $dst|$dst, $src}", []>; def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(set R8:$dst, imm:$src)]>; @@ -358,85 +362,88 @@ def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", []>; def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), - "mov{b} {$src, $dst|$dst, $src}">; + "mov{b} {$src, $dst|$dst, $src}", []>; def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), - "mov{w} {$src, $dst|$dst, $src}">, OpSize; + "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), - "mov{l} {$src, $dst|$dst, $src}">; + "mov{l} {$src, $dst|$dst, $src}", []>; def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), - "mov{b} {$src, $dst|$dst, $src}">; + "mov{b} {$src, $dst|$dst, $src}", []>; def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), - "mov{w} {$src, $dst|$dst, $src}">, OpSize; + "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), - "mov{l} {$src, $dst|$dst, $src}">; + "mov{l} {$src, $dst|$dst, $src}", []>; //===----------------------------------------------------------------------===// // Fixed-Register Multiplication and Division Instructions... // // Extra precision multiplication -def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">, +def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*R8 -def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">, +def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">, +def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), - "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] + "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), - "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] + "mul{w} $src", []>, Imp<[AX],[AX,DX]>, + OpSize; // AX,DX = AX*[mem16] def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), - "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] + "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] -def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src">, +def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*R8 -def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src">, +def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src">, +def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), - "imul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] + "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), - "imul{w} $src">, Imp<[AX],[AX,DX]>, OpSize;// AX,DX = AX*[mem16] + "imul{w} $src", []>, Imp<[AX],[AX,DX]>, + OpSize; // AX,DX = AX*[mem16] def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), - "imul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] + "imul{l} $src", []>, + Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH - "div{b} $src">, Imp<[AX],[AX]>; + "div{b} $src", []>, Imp<[AX],[AX]>; def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX - "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; + "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX - "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH - "div{b} $src">, Imp<[AX],[AX]>; + "div{b} $src", []>, Imp<[AX],[AX]>; def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX - "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; + "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX - "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; // Signed division/remainder. def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH - "idiv{b} $src">, Imp<[AX],[AX]>; + "idiv{b} $src", []>, Imp<[AX],[AX]>; def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX - "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; + "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX - "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH - "idiv{b} $src">, Imp<[AX],[AX]>; + "idiv{b} $src", []>, Imp<[AX],[AX]>; def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX - "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; + "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX - "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; // Sign-extenders for division. def CBW : I<0x98, RawFrm, (ops), - "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL) + "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL) def CWD : I<0x99, RawFrm, (ops), - "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX) + "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX) def CDQ : I<0x99, RawFrm, (ops), - "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) + "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) //===----------------------------------------------------------------------===// @@ -447,252 +454,265 @@ let isTwoAddress = 1 in { // Conditional moves def CMOVB16rr : I<0x42, MRMSrcReg, // if , TB, OpSize; + "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVB16rm : I<0x42, MRMSrcMem, // if , TB, OpSize; + "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVB32rr : I<0x42, MRMSrcReg, // if , TB; + "cmovb {$src2, $dst|$dst, $src2}", []>, TB; def CMOVB32rm : I<0x42, MRMSrcMem, // if , TB; + "cmovb {$src2, $dst|$dst, $src2}", []>, TB; def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovae {$src2, $dst|$dst, $src2}">, TB; + "cmovae {$src2, $dst|$dst, $src2}", []>, TB; def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovae {$src2, $dst|$dst, $src2}">, TB; + "cmovae {$src2, $dst|$dst, $src2}", []>, TB; def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmove {$src2, $dst|$dst, $src2}">, TB; + "cmove {$src2, $dst|$dst, $src2}", []>, TB; def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmove {$src2, $dst|$dst, $src2}">, TB; + "cmove {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovne {$src2, $dst|$dst, $src2}">, TB; + "cmovne {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovne {$src2, $dst|$dst, $src2}">, TB; + "cmovne {$src2, $dst|$dst, $src2}", []>, TB; def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovbe {$src2, $dst|$dst, $src2}">, TB; + "cmovbe {$src2, $dst|$dst, $src2}", []>, TB; def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovbe {$src2, $dst|$dst, $src2}">, TB; + "cmovbe {$src2, $dst|$dst, $src2}", []>, TB; def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmova {$src2, $dst|$dst, $src2}">, TB; + "cmova {$src2, $dst|$dst, $src2}", []>, TB; def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmova {$src2, $dst|$dst, $src2}">, TB; + "cmova {$src2, $dst|$dst, $src2}", []>, TB; def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovs {$src2, $dst|$dst, $src2}">, TB; + "cmovs {$src2, $dst|$dst, $src2}", []>, TB; def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovs {$src2, $dst|$dst, $src2}">, TB; + "cmovs {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovns {$src2, $dst|$dst, $src2}">, TB; + "cmovns {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovns {$src2, $dst|$dst, $src2}">, TB; + "cmovns {$src2, $dst|$dst, $src2}", []>, TB; def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovp {$src2, $dst|$dst, $src2}">, TB; + "cmovp {$src2, $dst|$dst, $src2}", []>, TB; def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovp {$src2, $dst|$dst, $src2}">, TB; + "cmovp {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovnp {$src2, $dst|$dst, $src2}">, TB; + "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovnp {$src2, $dst|$dst, $src2}">, TB; + "cmovnp {$src2, $dst|$dst, $src2}", []>, TB; def CMOVL16rr : I<0x4C, MRMSrcReg, // if , TB, OpSize; + "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVL16rm : I<0x4C, MRMSrcMem, // if , TB, OpSize; + "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVL32rr : I<0x4C, MRMSrcReg, // if , TB; + "cmovl {$src2, $dst|$dst, $src2}", []>, TB; def CMOVL32rm : I<0x4C, MRMSrcMem, // if , TB; + "cmovl {$src2, $dst|$dst, $src2}", []>, TB; def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovge {$src2, $dst|$dst, $src2}">, TB; + "cmovge {$src2, $dst|$dst, $src2}", []>, TB; def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovge {$src2, $dst|$dst, $src2}">, TB; + "cmovge {$src2, $dst|$dst, $src2}", []>, TB; def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovle {$src2, $dst|$dst, $src2}">, TB; + "cmovle {$src2, $dst|$dst, $src2}", []>, TB; def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovle {$src2, $dst|$dst, $src2}">, TB; + "cmovle {$src2, $dst|$dst, $src2}", []>, TB; def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 (ops R16:$dst, R16:$src1, R16:$src2), - "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; + "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 (ops R32:$dst, R32:$src1, R32:$src2), - "cmovg {$src2, $dst|$dst, $src2}">, TB; + "cmovg {$src2, $dst|$dst, $src2}", []>, TB; def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovg {$src2, $dst|$dst, $src2}">, TB; + "cmovg {$src2, $dst|$dst, $src2}", []>, TB; // unary instructions -def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">; -def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize; -def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">; +def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", + [(set R8:$dst, (ineg R8:$src))]>; +def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", + [(set R16:$dst, (ineg R16:$src))]>, OpSize; +def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", + [(set R32:$dst, (ineg R32:$src))]>; let isTwoAddress = 0 in { - def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">; - def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize; - def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">; + def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", []>; + def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst", []>, OpSize; + def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst", []>; } -def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">; -def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize; -def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">; +def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", + [(set R8:$dst, (not R8:$src))]>; +def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", + [(set R16:$dst, (not R16:$src))]>, OpSize; +def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", + [(set R32:$dst, (not R32:$src))]>; let isTwoAddress = 0 in { - def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">; - def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize; - def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">; + def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", []>; + def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst", []>, OpSize; + def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", []>; } -def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">; +def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", + [(set R8:$dst, (add R8:$src, 1))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize; -def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">; +def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", + [(set R16:$dst, (add R16:$src, 1))]>, OpSize; +def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", + [(set R32:$dst, (add R32:$src, 1))]>; } let isTwoAddress = 0 in { - def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">; - def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize; - def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">; + def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", []>; + def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst", []>, OpSize; + def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>; } -def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">; +def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", []>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize; -def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">; +def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", []>, + OpSize; +def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", []>; } let isTwoAddress = 0 in { - def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">; - def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize; - def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">; + def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst", []>; + def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst", []>, OpSize; + def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst", []>; } // Logical operators... let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y def AND8rr : I<0x20, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), - "and{b} {$src2, $dst|$dst, $src2}">; + "and{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (and R8:$src1, R8:$src2))]>; def AND16rr : I<0x21, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "and{w} {$src2, $dst|$dst, $src2}">, OpSize; + "and{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; def AND32rr : I<0x21, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "and{l} {$src2, $dst|$dst, $src2}">; + "and{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (and R32:$src1, R32:$src2))]>; } def AND8rm : I<0x22, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), - "and{b} {$src2, $dst|$dst, $src2}">; + "and{b} {$src2, $dst|$dst, $src2}",[]>; def AND16rm : I<0x23, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "and{w} {$src2, $dst|$dst, $src2}">, OpSize; + "and{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def AND32rm : I<0x23, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "and{l} {$src2, $dst|$dst, $src2}">; + "and{l} {$src2, $dst|$dst, $src2}", []>; def AND8ri : Ii8<0x80, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm :$src2), @@ -718,13 +738,13 @@ def AND32ri8 : Ii8<0x83, MRM4r, let isTwoAddress = 0 in { def AND8mr : I<0x20, MRMDestMem, (ops i8mem :$dst, R8 :$src), - "and{b} {$src, $dst|$dst, $src}">; + "and{b} {$src, $dst|$dst, $src}", []>; def AND16mr : I<0x21, MRMDestMem, (ops i16mem:$dst, R16:$src), - "and{w} {$src, $dst|$dst, $src}">, OpSize; + "and{w} {$src, $dst|$dst, $src}", []>, OpSize; def AND32mr : I<0x21, MRMDestMem, (ops i32mem:$dst, R32:$src), - "and{l} {$src, $dst|$dst, $src}">; + "and{l} {$src, $dst|$dst, $src}", []>; def AND8mi : Ii8<0x80, MRM4m, (ops i8mem :$dst, i8imm :$src), "and{b} {$src, $dst|$dst, $src}", []>; @@ -745,18 +765,21 @@ let isTwoAddress = 0 in { let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), - "or{b} {$src2, $dst|$dst, $src2}">; + "or{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (or R8:$src1, R8:$src2))]>; def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "or{w} {$src2, $dst|$dst, $src2}">, OpSize; + "or{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "or{l} {$src2, $dst|$dst, $src2}">; + "or{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (or R32:$src1, R32:$src2))]>; } def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), - "or{b} {$src2, $dst|$dst, $src2}">; + "or{b} {$src2, $dst|$dst, $src2}", []>; def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), - "or{w} {$src2, $dst|$dst, $src2}">, OpSize; + "or{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), - "or{l} {$src2, $dst|$dst, $src2}">; + "or{l} {$src2, $dst|$dst, $src2}", []>; def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "or{b} {$src2, $dst|$dst, $src2}", @@ -776,11 +799,11 @@ def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), [(set R32:$dst, (or R32:$src1, immSExt8:$src2))]>; let isTwoAddress = 0 in { def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), - "or{b} {$src, $dst|$dst, $src}">; + "or{b} {$src, $dst|$dst, $src}", []>; def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), - "or{w} {$src, $dst|$dst, $src}">, OpSize; + "or{w} {$src, $dst|$dst, $src}", []>, OpSize; def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), - "or{l} {$src, $dst|$dst, $src}">; + "or{l} {$src, $dst|$dst, $src}", []>; def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), "or{b} {$src, $dst|$dst, $src}", []>; def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), @@ -797,24 +820,27 @@ let isTwoAddress = 0 in { let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y def XOR8rr : I<0x30, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), - "xor{b} {$src2, $dst|$dst, $src2}">; + "xor{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; def XOR16rr : I<0x31, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; + "xor{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; def XOR32rr : I<0x31, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "xor{l} {$src2, $dst|$dst, $src2}">; + "xor{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; } def XOR8rm : I<0x32, MRMSrcMem , (ops R8 :$dst, R8:$src1, i8mem :$src2), - "xor{b} {$src2, $dst|$dst, $src2}">; + "xor{b} {$src2, $dst|$dst, $src2}", []>; def XOR16rm : I<0x33, MRMSrcMem , (ops R16:$dst, R8:$src1, i16mem:$src2), - "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; + "xor{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def XOR32rm : I<0x33, MRMSrcMem , (ops R32:$dst, R8:$src1, i32mem:$src2), - "xor{l} {$src2, $dst|$dst, $src2}">; + "xor{l} {$src2, $dst|$dst, $src2}", []>; def XOR8ri : Ii8<0x80, MRM6r, (ops R8:$dst, R8:$src1, i8imm:$src2), @@ -839,13 +865,13 @@ def XOR32ri8 : Ii8<0x83, MRM6r, let isTwoAddress = 0 in { def XOR8mr : I<0x30, MRMDestMem, (ops i8mem :$dst, R8 :$src), - "xor{b} {$src, $dst|$dst, $src}">; + "xor{b} {$src, $dst|$dst, $src}", []>; def XOR16mr : I<0x31, MRMDestMem, (ops i16mem:$dst, R16:$src), - "xor{w} {$src, $dst|$dst, $src}">, OpSize; + "xor{w} {$src, $dst|$dst, $src}", []>, OpSize; def XOR32mr : I<0x31, MRMDestMem, (ops i32mem:$dst, R32:$src), - "xor{l} {$src, $dst|$dst, $src}">; + "xor{l} {$src, $dst|$dst, $src}", []>; def XOR8mi : Ii8<0x80, MRM6m, (ops i8mem :$dst, i8imm :$src), "xor{b} {$src, $dst|$dst, $src}", []>; @@ -866,11 +892,11 @@ let isTwoAddress = 0 in { // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), - "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), - "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), - "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "shl{b} {$src2, $dst|$dst, $src2}", @@ -886,25 +912,25 @@ def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), let isTwoAddress = 0 in { def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), - "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shl{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), - "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "shl{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), - "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shl{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), - "shl{b} {$src, $dst|$dst, $src}", []>; + "shl{b} {$src, $dst|$dst, $src}, []", []>; def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), - "shl{w} {$src, $dst|$dst, $src}", []>, OpSize; + "shl{w} {$src, $dst|$dst, $src}, []", []>, OpSize; def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), - "shl{l} {$src, $dst|$dst, $src}", []>; + "shl{l} {$src, $dst|$dst, $src}, []", []>; } def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), - "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), - "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), - "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "shr{b} {$src2, $dst|$dst, $src2}", @@ -918,11 +944,11 @@ def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), let isTwoAddress = 0 in { def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), - "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), - "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), - "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), "shr{b} {$src, $dst|$dst, $src}", []>; def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), @@ -932,11 +958,11 @@ let isTwoAddress = 0 in { } def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), - "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), - "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), - "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "sar{b} {$src2, $dst|$dst, $src2}", @@ -949,11 +975,11 @@ def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), [(set R32:$dst, (sra R32:$src1, immSExt8:$src2))]>; let isTwoAddress = 0 in { def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), - "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), - "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), - "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), "sar{b} {$src, $dst|$dst, $src}", []>; def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), @@ -965,11 +991,11 @@ let isTwoAddress = 0 in { // Rotate instructions // FIXME: provide shorter instructions when imm8 == 1 def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), - "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), - "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), - "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "rol{b} {$src2, $dst|$dst, $src2}", []>; @@ -980,11 +1006,11 @@ def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), let isTwoAddress = 0 in { def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), - "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), - "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), - "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), "rol{b} {$src, $dst|$dst, $src}", []>; def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), @@ -994,11 +1020,11 @@ let isTwoAddress = 0 in { } def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), - "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), - "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), - "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), "ror{b} {$src2, $dst|$dst, $src2}", []>; @@ -1008,11 +1034,11 @@ def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), "ror{l} {$src2, $dst|$dst, $src2}", []>; let isTwoAddress = 0 in { def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), - "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), - "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize; def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), - "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>; def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), "ror{b} {$src, $dst|$dst, $src}", []>; def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), @@ -1026,16 +1052,16 @@ let isTwoAddress = 0 in { // Double shift instructions (generalizations of rotate) def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB, OpSize; def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB, OpSize; let isCommutable = 1 in { // These instructions commute to each other. @@ -1057,10 +1083,10 @@ def SHRD16rri8 : Ii8<0xAC, MRMDestReg, let isTwoAddress = 0 in { def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB; def SHLD32mri8 : Ii8<0xA4, MRMDestMem, (ops i32mem:$dst, R32:$src2, i8imm:$src3), @@ -1072,10 +1098,10 @@ let isTwoAddress = 0 in { TB; def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), - "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB, OpSize; def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), - "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>, Imp<[CL],[]>, TB, OpSize; def SHLD16mri8 : Ii8<0xA4, MRMDestMem, (ops i16mem:$dst, R16:$src2, i8imm:$src3), @@ -1091,20 +1117,23 @@ let isTwoAddress = 0 in { // Arithmetic. let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), - "add{b} {$src2, $dst|$dst, $src2}">; + "add{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (add R8:$src1, R8:$src2))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "add{l} {$src2, $dst|$dst, $src2}">; + "add{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (add R32:$src1, R32:$src2))]>; } // end isConvertibleToThreeAddress } // end isCommutable def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), - "add{b} {$src2, $dst|$dst, $src2}">; + "add{b} {$src2, $dst|$dst, $src2}", []>; def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "add{l} {$src2, $dst|$dst, $src2}">; + "add{l} {$src2, $dst|$dst, $src2}", []>; def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), "add{b} {$src2, $dst|$dst, $src2}", @@ -1129,11 +1158,11 @@ def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), let isTwoAddress = 0 in { def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), - "add{b} {$src2, $dst|$dst, $src2}">; + "add{b} {$src2, $dst|$dst, $src2}", []>; def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), - "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + "add{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "add{l} {$src2, $dst|$dst, $src2}">; + "add{l} {$src2, $dst|$dst, $src2}", []>; def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), "add{b} {$src2, $dst|$dst, $src2}", []>; def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), @@ -1148,10 +1177,10 @@ let isTwoAddress = 0 in { let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "adc{l} {$src2, $dst|$dst, $src2}">; + "adc{l} {$src2, $dst|$dst, $src2}", []>; } def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), - "adc{l} {$src2, $dst|$dst, $src2}">; + "adc{l} {$src2, $dst|$dst, $src2}", []>; def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", []>; def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), @@ -1159,7 +1188,7 @@ def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), let isTwoAddress = 0 in { def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "adc{l} {$src2, $dst|$dst, $src2}">; + "adc{l} {$src2, $dst|$dst, $src2}", []>; def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", []>; def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), @@ -1167,17 +1196,20 @@ let isTwoAddress = 0 in { } def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), - "sub{b} {$src2, $dst|$dst, $src2}">; + "sub{b} {$src2, $dst|$dst, $src2}", + [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), - "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sub{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "sub{l} {$src2, $dst|$dst, $src2}">; + "sub{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), - "sub{b} {$src2, $dst|$dst, $src2}">; + "sub{b} {$src2, $dst|$dst, $src2}", []>; def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "sub{l} {$src2, $dst|$dst, $src2}">; + "sub{l} {$src2, $dst|$dst, $src2}", []>; def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", @@ -1196,11 +1228,11 @@ def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), [(set R32:$dst, (sub R32:$src1, immSExt8:$src2))]>; let isTwoAddress = 0 in { def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), - "sub{b} {$src2, $dst|$dst, $src2}">; + "sub{b} {$src2, $dst|$dst, $src2}", []>; def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), - "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + "sub{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "sub{l} {$src2, $dst|$dst, $src2}">; + "sub{l} {$src2, $dst|$dst, $src2}", []>; def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", []>; def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), @@ -1214,11 +1246,11 @@ let isTwoAddress = 0 in { } def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), - "sbb{l} {$src2, $dst|$dst, $src2}">; + "sbb{l} {$src2, $dst|$dst, $src2}", []>; let isTwoAddress = 0 in { def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), - "sbb{l} {$src2, $dst|$dst, $src2}">; + "sbb{l} {$src2, $dst|$dst, $src2}", []>; def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), "sbb{b} {$src2, $dst|$dst, $src2}", []>; def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), @@ -1236,7 +1268,7 @@ def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize; def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "sbb{l} {$src2, $dst|$dst, $src2}">; + "sbb{l} {$src2, $dst|$dst, $src2}", []>; def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", []>; @@ -1247,14 +1279,16 @@ def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2), let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; + "imul{w} {$src2, $dst|$dst, $src2}", + [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "imul{l} {$src2, $dst|$dst, $src2}">, TB; + "imul{l} {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; } def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; + "imul{w} {$src2, $dst|$dst, $src2}", []>, TB, OpSize; def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "imul{l} {$src2, $dst|$dst, $src2}">, TB; + "imul{l} {$src2, $dst|$dst, $src2}", []>, TB; } // end Two Address instructions @@ -1295,24 +1329,24 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 // let isCommutable = 1 in { // TEST X, Y --> TEST Y, X def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), - "test{b} {$src2, $src1|$src1, $src2}">; + "test{b} {$src2, $src1|$src1, $src2}", []>; def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), - "test{w} {$src2, $src1|$src1, $src2}">, OpSize; + "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), - "test{l} {$src2, $src1|$src1, $src2}">; + "test{l} {$src2, $src1|$src1, $src2}", []>; } def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), - "test{b} {$src2, $src1|$src1, $src2}">; + "test{b} {$src2, $src1|$src1, $src2}", []>; def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), - "test{w} {$src2, $src1|$src1, $src2}">, OpSize; + "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), - "test{l} {$src2, $src1|$src1, $src2}">; + "test{l} {$src2, $src1|$src1, $src2}", []>; def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), - "test{b} {$src2, $src1|$src1, $src2}">; + "test{b} {$src2, $src1|$src1, $src2}", []>; def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), - "test{w} {$src2, $src1|$src1, $src2}">, OpSize; + "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), - "test{l} {$src2, $src1|$src1, $src2}">; + "test{l} {$src2, $src1|$src1, $src2}", []>; def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 (ops R8:$src1, i8imm:$src2), @@ -1336,94 +1370,94 @@ def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 // Condition code ops, incl. set if equal/not equal/... -def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH -def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags +def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH +def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags def SETBr : I<0x92, MRM0r, - (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign + (ops R8 :$dst), "setb $dst", []>, TB; // R8 = < unsign def SETBm : I<0x92, MRM0m, - (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign + (ops i8mem:$dst), "setb $dst", []>, TB; // [mem8] = < unsign def SETAEr : I<0x93, MRM0r, - (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign + (ops R8 :$dst), "setae $dst", []>, TB; // R8 = >= unsign def SETAEm : I<0x93, MRM0m, - (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign + (ops i8mem:$dst), "setae $dst", []>, TB; // [mem8] = >= unsign def SETEr : I<0x94, MRM0r, - (ops R8 :$dst), "sete $dst">, TB; // R8 = == + (ops R8 :$dst), "sete $dst", []>, TB; // R8 = == def SETEm : I<0x94, MRM0m, - (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = == + (ops i8mem:$dst), "sete $dst", []>, TB; // [mem8] = == def SETNEr : I<0x95, MRM0r, - (ops R8 :$dst), "setne $dst">, TB; // R8 = != + (ops R8 :$dst), "setne $dst", []>, TB; // R8 = != def SETNEm : I<0x95, MRM0m, - (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = != + (ops i8mem:$dst), "setne $dst", []>, TB; // [mem8] = != def SETBEr : I<0x96, MRM0r, - (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign + (ops R8 :$dst), "setbe $dst", []>, TB; // R8 = <= unsign def SETBEm : I<0x96, MRM0m, - (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign + (ops i8mem:$dst), "setbe $dst", []>, TB; // [mem8] = <= unsign def SETAr : I<0x97, MRM0r, - (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed + (ops R8 :$dst), "seta $dst", []>, TB; // R8 = > signed def SETAm : I<0x97, MRM0m, - (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed + (ops i8mem:$dst), "seta $dst", []>, TB; // [mem8] = > signed def SETSr : I<0x98, MRM0r, - (ops R8 :$dst), "sets $dst">, TB; // R8 = + (ops R8 :$dst), "sets $dst", []>, TB; // R8 = def SETSm : I<0x98, MRM0m, - (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = + (ops i8mem:$dst), "sets $dst", []>, TB; // [mem8] = def SETNSr : I<0x99, MRM0r, - (ops R8 :$dst), "setns $dst">, TB; // R8 = ! + (ops R8 :$dst), "setns $dst", []>, TB; // R8 = ! def SETNSm : I<0x99, MRM0m, - (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = ! + (ops i8mem:$dst), "setns $dst", []>, TB; // [mem8] = ! def SETPr : I<0x9A, MRM0r, - (ops R8 :$dst), "setp $dst">, TB; // R8 = parity + (ops R8 :$dst), "setp $dst", []>, TB; // R8 = parity def SETPm : I<0x9A, MRM0m, - (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity + (ops i8mem:$dst), "setp $dst", []>, TB; // [mem8] = parity def SETNPr : I<0x9B, MRM0r, - (ops R8 :$dst), "setnp $dst">, TB; // R8 = not parity + (ops R8 :$dst), "setnp $dst", []>, TB; // R8 = not parity def SETNPm : I<0x9B, MRM0m, - (ops i8mem:$dst), "setnp $dst">, TB; // [mem8] = not parity + (ops i8mem:$dst), "setnp $dst", []>, TB; // [mem8] = not parity def SETLr : I<0x9C, MRM0r, - (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed + (ops R8 :$dst), "setl $dst", []>, TB; // R8 = < signed def SETLm : I<0x9C, MRM0m, - (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed + (ops i8mem:$dst), "setl $dst", []>, TB; // [mem8] = < signed def SETGEr : I<0x9D, MRM0r, - (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed + (ops R8 :$dst), "setge $dst", []>, TB; // R8 = >= signed def SETGEm : I<0x9D, MRM0m, - (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed + (ops i8mem:$dst), "setge $dst", []>, TB; // [mem8] = >= signed def SETLEr : I<0x9E, MRM0r, - (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed + (ops R8 :$dst), "setle $dst", []>, TB; // R8 = <= signed def SETLEm : I<0x9E, MRM0m, - (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed + (ops i8mem:$dst), "setle $dst", []>, TB; // [mem8] = <= signed def SETGr : I<0x9F, MRM0r, - (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed + (ops R8 :$dst), "setg $dst", []>, TB; // R8 = < signed def SETGm : I<0x9F, MRM0m, - (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed + (ops i8mem:$dst), "setg $dst", []>, TB; // [mem8] = < signed // Integer comparisons def CMP8rr : I<0x38, MRMDestReg, (ops R8 :$src1, R8 :$src2), - "cmp{b} {$src2, $src1|$src1, $src2}">; + "cmp{b} {$src2, $src1|$src1, $src2}", []>; def CMP16rr : I<0x39, MRMDestReg, (ops R16:$src1, R16:$src2), - "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; + "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def CMP32rr : I<0x39, MRMDestReg, (ops R32:$src1, R32:$src2), - "cmp{l} {$src2, $src1|$src1, $src2}">; + "cmp{l} {$src2, $src1|$src1, $src2}", []>; def CMP8mr : I<0x38, MRMDestMem, (ops i8mem :$src1, R8 :$src2), - "cmp{b} {$src2, $src1|$src1, $src2}">; + "cmp{b} {$src2, $src1|$src1, $src2}", []>; def CMP16mr : I<0x39, MRMDestMem, (ops i16mem:$src1, R16:$src2), - "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; + "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def CMP32mr : I<0x39, MRMDestMem, (ops i32mem:$src1, R32:$src2), - "cmp{l} {$src2, $src1|$src1, $src2}">; + "cmp{l} {$src2, $src1|$src1, $src2}", []>; def CMP8rm : I<0x3A, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), - "cmp{b} {$src2, $src1|$src1, $src2}">; + "cmp{b} {$src2, $src1|$src1, $src2}", []>; def CMP16rm : I<0x3B, MRMSrcMem, (ops R16:$src1, i16mem:$src2), - "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; + "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize; def CMP32rm : I<0x3B, MRMSrcMem, (ops R32:$src1, i32mem:$src2), - "cmp{l} {$src2, $src1|$src1, $src2}">; + "cmp{l} {$src2, $src1|$src1, $src2}", []>; def CMP8ri : Ii8<0x80, MRM7r, (ops R16:$src1, i8imm:$src2), "cmp{b} {$src2, $src1|$src1, $src2}", []>; @@ -1445,171 +1479,193 @@ def CMP32mi : Ii32<0x81, MRM7m, // Sign/Zero extenders def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), - "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; + "movs{bw|x} {$src, $dst|$dst, $src}", + [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), - "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; + "movs{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), - "movs{bl|x} {$src, $dst|$dst, $src}">, TB; + "movs{bl|x} {$src, $dst|$dst, $src}", + [(set R32:$dst, (sext R8:$src))]>, TB; def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), - "movs{bl|x} {$src, $dst|$dst, $src}">, TB; + "movs{bl|x} {$src, $dst|$dst, $src}", []>, TB; def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), - "movs{wl|x} {$src, $dst|$dst, $src}">, TB; + "movs{wl|x} {$src, $dst|$dst, $src}", + [(set R32:$dst, (sext R16:$src))]>, TB; def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), - "movs{wl|x} {$src, $dst|$dst, $src}">, TB; + "movs{wl|x} {$src, $dst|$dst, $src}", []>, TB; def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), - "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; + "movz{bw|x} {$src, $dst|$dst, $src}", + [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), - "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; + "movz{bw|x} {$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), - "movz{bl|x} {$src, $dst|$dst, $src}">, TB; + "movz{bl|x} {$src, $dst|$dst, $src}", + [(set R32:$dst, (zext R8:$src))]>, TB; def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), - "movz{bl|x} {$src, $dst|$dst, $src}">, TB; + "movz{bl|x} {$src, $dst|$dst, $src}", []>, TB; def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), - "movz{wl|x} {$src, $dst|$dst, $src}">, TB; + "movz{wl|x} {$src, $dst|$dst, $src}", + [(set R32:$dst, (zext R16:$src))]>, TB; def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), - "movz{wl|x} {$src, $dst|$dst, $src}">, TB; + "movz{wl|x} {$src, $dst|$dst, $src}", []>, TB; //===----------------------------------------------------------------------===// // XMM Floating point support (requires SSE2) //===----------------------------------------------------------------------===// def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), - "movss {$src, $dst|$dst, $src}">, XS; + "movss {$src, $dst|$dst, $src}", []>, XS; def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), - "movss {$src, $dst|$dst, $src}">, XS; + "movss {$src, $dst|$dst, $src}", []>, XS; def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src), - "movss {$src, $dst|$dst, $src}">, XS; + "movss {$src, $dst|$dst, $src}", []>, XS; def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), - "movsd {$src, $dst|$dst, $src}">, XD; + "movsd {$src, $dst|$dst, $src}", []>, XD; def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), - "movsd {$src, $dst|$dst, $src}">, XD; + "movsd {$src, $dst|$dst, $src}", []>, XD; def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src), - "movsd {$src, $dst|$dst, $src}">, XD; + "movsd {$src, $dst|$dst, $src}", []>, XD; def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src), - "cvttsd2si {$src, $dst|$dst, $src}">, XD; + "cvttsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD; def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), - "cvttsd2si {$src, $dst|$dst, $src}">, XD; + "cvttsd2si {$src, $dst|$dst, $src}", []>, XD; def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src), - "cvttss2si {$src, $dst|$dst, $src}">, XS; + "cvttss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS; def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), - "cvttss2si {$src, $dst|$dst, $src}">, XS; + "cvttss2si {$src, $dst|$dst, $src}", []>, XS; def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src), - "cvtsd2ss {$src, $dst|$dst, $src}">, XS; + "cvtsd2ss {$src, $dst|$dst, $src}", + [(set V4F4:$dst, (fround V2F8:$src))]>, XS; def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src), - "cvtsd2ss {$src, $dst|$dst, $src}">, XS; + "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS; def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src), - "cvtss2sd {$src, $dst|$dst, $src}">, XD; + "cvtss2sd {$src, $dst|$dst, $src}", + [(set V2F8:$dst, (fextend V4F4:$src))]>, XD; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src), - "cvtss2sd {$src, $dst|$dst, $src}">, XD; + "cvtss2sd {$src, $dst|$dst, $src}", []>, XD; def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src), - "cvtsi2ss {$src, $dst|$dst, $src}">, XS; + "cvtsi2ss {$src, $dst|$dst, $src}", + [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS; def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src), - "cvtsi2ss {$src, $dst|$dst, $src}">, XS; + "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS; def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src), - "cvtsi2sd {$src, $dst|$dst, $src}">, XD; + "cvtsi2sd {$src, $dst|$dst, $src}", + [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD; def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src), - "cvtsi2sd {$src, $dst|$dst, $src}">, XD; + "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD; def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), - "subss {$src, $dst|$dst, $src}">, XS; + "sqrtss {$src, $dst|$dst, $src}", []>, XS; def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), - "subss {$src, $dst|$dst, $src}">, XS; + "sqrtss {$src, $dst|$dst, $src}", + [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS; def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), - "subsd {$src, $dst|$dst, $src}">, XD; + "sqrtsd {$src, $dst|$dst, $src}", []>, XD; def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), - "subsd {$src, $dst|$dst, $src}">, XD; + "sqrtsd {$src, $dst|$dst, $src}", + [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD; def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src), - "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize; + "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize; def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src), - "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize; + "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize; def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src), - "ucomiss {$src, $dst|$dst, $src}">, TB; + "ucomiss {$src, $dst|$dst, $src}", []>, TB; def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src), - "ucomiss {$src, $dst|$dst, $src}">, TB; + "ucomiss {$src, $dst|$dst, $src}", []>, TB; -// Pseudo-instructions that map to fld0 to xorps/xorpd for sse. +// Pseudo-instructions that map fld0 to xorps/xorpd for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst), - "xorps $dst, $dst">, TB; + "xorps $dst, $dst", []>, TB; def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst), - "xorpd $dst, $dst">, TB, OpSize; + "xorpd $dst, $dst", []>, TB, OpSize; let isTwoAddress = 1 in { let isCommutable = 1 in { -def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "addss {$src, $dst|$dst, $src}">, XS; -def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "addsd {$src, $dst|$dst, $src}">, XD; -def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "andps {$src, $dst|$dst, $src}">, TB; -def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "andpd {$src, $dst|$dst, $src}">, TB, OpSize; -def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "mulss {$src, $dst|$dst, $src}">, XS; -def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "mulsd {$src, $dst|$dst, $src}">, XD; -def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "orps {$src, $dst|$dst, $src}">, TB; -def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "orpd {$src, $dst|$dst, $src}">, TB, OpSize; -def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "xorps {$src, $dst|$dst, $src}">, TB; -def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "xorpd {$src, $dst|$dst, $src}">, TB, OpSize; +def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "addss {$src2, $dst|$dst, $src2}", + [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS; +def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "addsd {$src2, $dst|$dst, $src2}", + [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD; +def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "andps {$src2, $dst|$dst, $src2}", []>, TB; +def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; +def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "mulss {$src2, $dst|$dst, $src2}", + [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS; +def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "mulsd {$src2, $dst|$dst, $src2}", + [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD; +def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "orps {$src2, $dst|$dst, $src2}", []>, TB; +def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; +def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "xorps {$src2, $dst|$dst, $src2}", []>, TB; +def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; } -def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "andnps {$src, $dst|$dst, $src}">, TB; -def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "andnpd {$src, $dst|$dst, $src}">, TB, OpSize; -def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src), - "addss {$src, $dst|$dst, $src}">, XS; -def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src), - "addsd {$src, $dst|$dst, $src}">, XD; -def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src), - "mulss {$src, $dst|$dst, $src}">, XS; -def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src), - "mulsd {$src, $dst|$dst, $src}">, XD; +def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "andnps {$src2, $dst|$dst, $src2}", []>, TB; +def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize; +def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), + "addss {$src2, $dst|$dst, $src2}", []>, XS; +def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), + "addsd {$src2, $dst|$dst, $src2}", []>, XD; +def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), + "mulss {$src2, $dst|$dst, $src2}", []>, XS; +def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), + "mulsd {$src2, $dst|$dst, $src2}", []>, XD; -def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src), - "divss {$src, $dst|$dst, $src}">, XS; -def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "divss {$src, $dst|$dst, $src}">, XS; -def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src), - "divsd {$src, $dst|$dst, $src}">, XD; -def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "divsd {$src, $dst|$dst, $src}">, XD; +def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), + "divss {$src2, $dst|$dst, $src2}", []>, XS; +def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "divss {$src2, $dst|$dst, $src2}", + [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS; +def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), + "divsd {$src2, $dst|$dst, $src2}", []>, XD; +def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "divsd {$src2, $dst|$dst, $src2}", + [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD; -def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src), - "subss {$src, $dst|$dst, $src}">, XS; -def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src), - "subss {$src, $dst|$dst, $src}">, XS; -def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src), - "subsd {$src, $dst|$dst, $src}">, XD; -def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src), - "subsd {$src, $dst|$dst, $src}">, XD; +def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2), + "subss {$src2, $dst|$dst, $src2}", []>, XS; +def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2), + "subss {$src2, $dst|$dst, $src2}", + [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS; +def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2), + "subsd {$src2, $dst|$dst, $src2}", []>, XD; +def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2), + "subsd {$src2, $dst|$dst, $src2}", + [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD; def CMPSSrr : I<0xC2, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc), - "cmp${cc}ss {$src, $dst|$dst, $src}">, XS; + "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS; def CMPSSrm : I<0xC2, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc), - "cmp${cc}ss {$src, $dst|$dst, $src}">, XS; + "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS; def CMPSDrr : I<0xC2, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc), - "cmp${cc}sd {$src, $dst|$dst, $src}">, XD; + "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD; def CMPSDrm : I<0xC2, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc), - "cmp${cc}sd {$src, $dst|$dst, $src}">, XD; + "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD; } //===----------------------------------------------------------------------===// // Miscellaneous Instructions //===----------------------------------------------------------------------===// -def RDTSC : I<0x31, RawFrm, (ops), "rdtsc">, TB, Imp<[],[EAX,EDX]>; +def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>; //===----------------------------------------------------------------------===// @@ -1849,16 +1905,16 @@ def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0) // Binary arithmetic operations... class FPST0rInst o, dag ops, string asm> - : I, D8 { + : I, D8 { list Uses = [ST0]; list Defs = [ST0]; } class FPrST0Inst o, dag ops, string asm> - : I, DC { + : I, DC { list Uses = [ST0]; } class FPrST0PInst o, dag ops, string asm> - : I, DE { + : I, DE { list Uses = [ST0]; } @@ -1913,24 +1969,24 @@ def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i) "fucom $reg">, DD, Imp<[ST0],[]>; def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop (ops RST:$reg, variable_ops), - "fucomp $reg">, DD, Imp<[ST0],[]>; + "fucomp $reg", []>, DD, Imp<[ST0],[]>; def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop (ops variable_ops), - "fucompp">, DA, Imp<[ST0],[]>; + "fucompp", []>, DA, Imp<[ST0],[]>; def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i) (ops RST:$reg, variable_ops), "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop (ops RST:$reg, variable_ops), - "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; + "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>; // Floating point flag ops def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags - (ops), "fnstsw">, DF, Imp<[],[AX]>; + (ops), "fnstsw", []>, DF, Imp<[],[AX]>; def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world - (ops i16mem:$dst), "fnstcw $dst">; + (ops i16mem:$dst), "fnstcw $dst", []>; def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] - (ops i16mem:$dst), "fldcw $dst">; + (ops i16mem:$dst), "fldcw $dst", []>;