From f0a0cddbcda344a90b7217b744c78dccec71851c Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 18 Oct 2007 22:40:57 +0000 Subject: [PATCH] - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 12 ++++++++++-- lib/Target/ARM/ARMRegisterInfo.cpp | 4 ++-- lib/Target/ARM/ARMRegisterInfo.h | 4 ++-- lib/Target/Alpha/AlphaRegisterInfo.cpp | 4 ++-- lib/Target/Alpha/AlphaRegisterInfo.h | 4 ++-- lib/Target/IA64/IA64RegisterInfo.cpp | 4 ++-- lib/Target/IA64/IA64RegisterInfo.h | 4 ++-- lib/Target/Mips/MipsRegisterInfo.cpp | 4 ++-- lib/Target/Mips/MipsRegisterInfo.h | 4 ++-- lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 ++-- lib/Target/PowerPC/PPCRegisterInfo.h | 4 ++-- lib/Target/Sparc/SparcRegisterInfo.cpp | 4 ++-- lib/Target/Sparc/SparcRegisterInfo.h | 4 ++-- lib/Target/X86/X86RegisterInfo.cpp | 18 ++++++++++++++++-- lib/Target/X86/X86RegisterInfo.h | 10 ++++++++-- 15 files changed, 58 insertions(+), 30 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 12b022e0f96..dd24f37fe5c 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -508,7 +508,7 @@ public: const TargetRegisterClass *RC) const = 0; virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const = 0; @@ -518,7 +518,7 @@ public: const TargetRegisterClass *RC) const = 0; virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const =0; @@ -577,6 +577,14 @@ public: return false; } + /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new + /// instruction after load / store are unfolded from the specified opcode. + /// It returns zero if the specified unfolding is impossible. + virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, + bool UnfoldLoad, bool UnfoldStore) const { + return 0; + } + /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue /// time). diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index c448467328d..e97d6d27884 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -183,7 +183,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; @@ -239,7 +239,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 26602527b2a..e0a2493d77f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -52,7 +52,7 @@ public: const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -62,7 +62,7 @@ public: const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index b62f9095c73..6dac374ff27 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -83,7 +83,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; @@ -128,7 +128,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index 467178de2b7..8cccacfcea9 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -34,7 +34,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -44,7 +44,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index c826d4c3170..b260b1b97fc 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -61,7 +61,7 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; @@ -113,7 +113,7 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index 3fcd213de12..b69b2854b97 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -35,7 +35,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -45,7 +45,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 8fd311196f1..cd61fe88304 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -96,7 +96,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { if (RC != Mips::CPURegsRegisterClass) @@ -128,7 +128,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { if (RC != Mips::CPURegsRegisterClass) diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 75ae4233919..9afc3b5dba5 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -38,7 +38,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -48,7 +48,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 122a8d3d3a2..421c0b11e7b 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -182,7 +182,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { if (Addr[0].isFrameIndex()) { @@ -291,7 +291,7 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { if (Addr[0].isFrameIndex()) { diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index b3f49d116a8..6b2a2cb19db 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -41,7 +41,7 @@ public: const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -51,7 +51,7 @@ public: const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 3055bf9dfe9..2402de65427 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -49,7 +49,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; @@ -91,7 +91,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 15a624f2634..01399100724 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -36,7 +36,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -46,7 +46,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 7788088685b..e88c050feba 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -806,7 +806,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = getStoreRegOpcode(RC); @@ -862,7 +862,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = getLoadRegOpcode(RC); @@ -1273,6 +1273,20 @@ X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, return true; } +unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, + bool UnfoldLoad, bool UnfoldStore) const { + DenseMap >::iterator I = + MemOp2RegOpTable.find((unsigned*)Opc); + if (I == MemOp2RegOpTable.end()) + return 0; + bool HasLoad = I->second.second & (1 << 4); + bool HasStore = I->second.second & (1 << 5); + if (UnfoldLoad && !HasLoad) + return 0; + if (UnfoldStore && !HasStore) + return 0; + return I->second.first; +} const unsigned * X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 76045476c2a..c21868c626f 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -89,7 +89,7 @@ public: const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -99,7 +99,7 @@ public: const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl Addr, + SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; @@ -142,6 +142,12 @@ public: bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl &NewNodes) const; + /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new + /// instruction after load / store are unfolded from the specified opcode. + /// It returns zero if the specified unfolding is impossible. + unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, + bool UnfoldLoad, bool UnfoldStore) const; + /// getCalleeSavedRegs - Return a null-terminated list of all of the /// callee-save registers on this target. const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;