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- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit

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versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-01-04 03:02:47 +00:00
parent cb9dd72fdc
commit f12e702a8c
2 changed files with 27 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -54,30 +54,6 @@ class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt,
CPU64Regs>;
// Jump and Link (Call)
let isCall=1, hasDelaySlot=1,
// All calls clobber the non-callee saved registers...
Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
class JumpLink64<bits<6> op, string instr_asm>:
FJ<op, (outs), (ins calltarget64:$target, variable_ops),
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
IIBranch>;
class JumpLinkReg64<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs), (ins CPU64Regs:$rs, variable_ops),
!strconcat(instr_asm, "\t$rs"),
[(MipsJmpLink CPU64Regs:$rs)], IIBranch> {
let rt = 0;
let rd = 31;
let shamt = 0;
}
class BranchLink64<string instr_asm>:
FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops),
!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
}
// Mul, Div
class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
@ -175,8 +151,6 @@ def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
/// Jump and Branch Instructions
def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
def JAL64 : JumpLink64<0x03, "jal">;
def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
@ -184,6 +158,15 @@ def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
// NOTE: These registers are N64's temporary registers. N32 has a different
// set of temporary registers.
let Defs = [AT_64, V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64, K0_64,
K1_64, D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, D6_64, D7_64,
D8_64, D9_64, D10_64, D11_64, D12_64, D13_64, D14_64, D15_64,
D16_64, D17_64, D18_64, D19_64, D20_64, D21_64, D22_64, D23_64] in
def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
/// Multiply and Divide Instructions.
def DMULT : Mult64<0x1c, "dmult", IIImul>;
def DMULTu : Mult64<0x1d, "dmultu", IIImul>;

34
lib/Target/Mips/MipsInstrInfo.td
View File

@ -522,26 +522,26 @@ class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
}
// Jump and Link (Call)
let isCall=1, hasDelaySlot=1,
// All calls clobber the non-callee saved registers...
Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
let isCall=1, hasDelaySlot=1 in {
class JumpLink<bits<6> op, string instr_asm>:
FJ<op, (outs), (ins calltarget:$target, variable_ops),
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
IIBranch>;
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
RegisterClass RC>:
FR<op, func, (outs), (ins RC:$rs, variable_ops),
!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
let rt = 0;
let rd = 31;
let shamt = 0;
}
class BranchLink<string instr_asm>:
FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
let rt = _rt;
}
}
// Mul, Div
@ -855,8 +855,6 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
/// Jump and Branch Instructions
def J : JumpFJ<0x02, "j">;
def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
def JAL : JumpLink<0x03, "jal">;
def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
def B : UncondBranch<0x04, "b">;
def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
def BNE : CBranch<0x05, "bne", setne, CPURegs>;
@ -865,10 +863,14 @@ def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
let rt=0x11 in
def BGEZAL : BranchLink<"bgezal">;
let rt=0x10 in
def BLTZAL : BranchLink<"bltzal">;
// All calls clobber the non-callee saved registers...
let Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
K0, K1, GP, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9] in {
def JAL : JumpLink<0x03, "jal">;
def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
}
let isReturn=1, isTerminator=1, hasDelaySlot=1,
isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in