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Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -301,6 +301,11 @@ public:
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const TargetRegisterClass *
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const TargetRegisterClass *
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getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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getAllocatableClass(const TargetRegisterClass *RC) const;
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// indicating if a register is allocatable or not. If a register class is
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/// indicating if a register is allocatable or not. If a register class is
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/// specified, returns the subset for the class.
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/// specified, returns the subset for the class.
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@ -114,8 +114,10 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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if (User->isMachineOpcode()) {
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if (User->isMachineOpcode()) {
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const MCInstrDesc &II = TII->get(User->getMachineOpcode());
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const MCInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC = 0;
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands())
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if (i+II.getNumDefs() < II.getNumOperands()) {
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RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
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RC = TRI->getAllocatableClass(
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TII->getRegClass(II, i+II.getNumDefs(), TRI));
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}
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if (!UseRC)
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if (!UseRC)
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UseRC = RC;
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UseRC = RC;
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else if (RC) {
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else if (RC) {
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@ -196,7 +198,8 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// is a vreg in the same register class, use the CopyToReg'd destination
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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unsigned VRBase = 0;
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const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
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const TargetRegisterClass *RC =
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TRI->getAllocatableClass(TII->getRegClass(II, i, TRI));
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if (II.OpInfo[i].isOptionalDef()) {
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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unsigned NumResults = CountResults(Node);
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@ -293,7 +296,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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if (II) {
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if (II) {
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const TargetRegisterClass *DstRC = 0;
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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if (IIOpNum < II->getNumOperands())
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DstRC = TII->getRegClass(*II, IIOpNum, TRI);
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DstRC = TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI));
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assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
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assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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"Don't have operand info for this instruction!");
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if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
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if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
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@ -548,7 +551,8 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
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// Create the new VReg in the destination class and emit a copy.
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// Create the new VReg in the destination class and emit a copy.
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
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const TargetRegisterClass *DstRC =
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TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
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unsigned NewVReg = MRI->createVirtualRegister(DstRC);
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unsigned NewVReg = MRI->createVirtualRegister(DstRC);
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BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
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BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
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NewVReg).addReg(VReg);
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NewVReg).addReg(VReg);
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@ -566,7 +570,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
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bool IsClone, bool IsCloned) {
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bool IsClone, bool IsCloned) {
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
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const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
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const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
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unsigned NewVReg = MRI->createVirtualRegister(RC);
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unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
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TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
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TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
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unsigned NumOps = Node->getNumOperands();
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unsigned NumOps = Node->getNumOperands();
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@ -1298,7 +1298,8 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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// Unfold the load.
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// Unfold the load.
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DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
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DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
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const TargetRegisterClass *RC =
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const TargetRegisterClass *RC =
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TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
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TRI->getAllocatableClass(
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TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI));
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unsigned Reg = MRI->createVirtualRegister(RC);
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unsigned Reg = MRI->createVirtualRegister(RC);
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SmallVector<MachineInstr *, 2> NewMIs;
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SmallVector<MachineInstr *, 2> NewMIs;
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if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
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if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
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@ -46,6 +46,29 @@ void PrintReg::print(raw_ostream &OS) const {
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}
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}
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}
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}
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
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if (!RC || RC->isAllocatable())
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return RC;
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const unsigned *SubClass = RC->getSubClassMask();
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for (unsigned Base = 0, BaseE = getNumRegClasses();
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Base < BaseE; Base += 32) {
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unsigned Idx = Base;
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for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
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unsigned Offset = CountTrailingZeros_32(Mask);
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const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
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if (SubRC->isAllocatable())
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return SubRC;
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Mask >>= Offset;
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Idx += Offset + 1;
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}
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}
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return NULL;
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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/// the right type that contains this physreg.
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@ -71,6 +94,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
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/// registers for the specific register class.
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/// registers for the specific register class.
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static void getAllocatableSetForRC(const MachineFunction &MF,
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static void getAllocatableSetForRC(const MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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const TargetRegisterClass *RC, BitVector &R){
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assert(RC->isAllocatable() && "invalid for nonallocatable sets");
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ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
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ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
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for (unsigned i = 0; i != Order.size(); ++i)
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for (unsigned i = 0; i != Order.size(); ++i)
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R.set(Order[i]);
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R.set(Order[i]);
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@ -80,7 +104,10 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(getNumRegs());
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BitVector Allocatable(getNumRegs());
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if (RC) {
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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// A register class with no allocatable subclass returns an empty set.
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const TargetRegisterClass *SubClass = getAllocatableClass(RC);
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if (SubClass)
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getAllocatableSetForRC(MF, SubClass, Allocatable);
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} else {
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} else {
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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E = regclass_end(); I != E; ++I)
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