mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e8cd3f2491
commit
f12f6dff97
@ -301,6 +301,11 @@ public:
|
||||
const TargetRegisterClass *
|
||||
getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
|
||||
|
||||
/// getAllocatableClass - Return the maximal subclass of the given register
|
||||
/// class that is alloctable, or NULL.
|
||||
const TargetRegisterClass *
|
||||
getAllocatableClass(const TargetRegisterClass *RC) const;
|
||||
|
||||
/// getAllocatableSet - Returns a bitset indexed by register number
|
||||
/// indicating if a register is allocatable or not. If a register class is
|
||||
/// specified, returns the subset for the class.
|
||||
|
@ -114,8 +114,10 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
|
||||
if (User->isMachineOpcode()) {
|
||||
const MCInstrDesc &II = TII->get(User->getMachineOpcode());
|
||||
const TargetRegisterClass *RC = 0;
|
||||
if (i+II.getNumDefs() < II.getNumOperands())
|
||||
RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
|
||||
if (i+II.getNumDefs() < II.getNumOperands()) {
|
||||
RC = TRI->getAllocatableClass(
|
||||
TII->getRegClass(II, i+II.getNumDefs(), TRI));
|
||||
}
|
||||
if (!UseRC)
|
||||
UseRC = RC;
|
||||
else if (RC) {
|
||||
@ -196,7 +198,8 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
|
||||
// is a vreg in the same register class, use the CopyToReg'd destination
|
||||
// register instead of creating a new vreg.
|
||||
unsigned VRBase = 0;
|
||||
const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
|
||||
const TargetRegisterClass *RC =
|
||||
TRI->getAllocatableClass(TII->getRegClass(II, i, TRI));
|
||||
if (II.OpInfo[i].isOptionalDef()) {
|
||||
// Optional def must be a physical register.
|
||||
unsigned NumResults = CountResults(Node);
|
||||
@ -293,7 +296,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
|
||||
if (II) {
|
||||
const TargetRegisterClass *DstRC = 0;
|
||||
if (IIOpNum < II->getNumOperands())
|
||||
DstRC = TII->getRegClass(*II, IIOpNum, TRI);
|
||||
DstRC = TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI));
|
||||
assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
|
||||
"Don't have operand info for this instruction!");
|
||||
if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
|
||||
@ -548,7 +551,8 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
|
||||
|
||||
// Create the new VReg in the destination class and emit a copy.
|
||||
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
||||
const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
|
||||
const TargetRegisterClass *DstRC =
|
||||
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
|
||||
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
|
||||
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
|
||||
NewVReg).addReg(VReg);
|
||||
@ -566,7 +570,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
|
||||
bool IsClone, bool IsCloned) {
|
||||
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
|
||||
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
|
||||
unsigned NewVReg = MRI->createVirtualRegister(RC);
|
||||
unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
|
||||
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
|
||||
TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
|
||||
unsigned NumOps = Node->getNumOperands();
|
||||
|
@ -1298,7 +1298,8 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
|
||||
// Unfold the load.
|
||||
DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
|
||||
const TargetRegisterClass *RC =
|
||||
TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
|
||||
TRI->getAllocatableClass(
|
||||
TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI));
|
||||
unsigned Reg = MRI->createVirtualRegister(RC);
|
||||
SmallVector<MachineInstr *, 2> NewMIs;
|
||||
if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
|
||||
|
@ -46,6 +46,29 @@ void PrintReg::print(raw_ostream &OS) const {
|
||||
}
|
||||
}
|
||||
|
||||
/// getAllocatableClass - Return the maximal subclass of the given register
|
||||
/// class that is alloctable, or NULL.
|
||||
const TargetRegisterClass *
|
||||
TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
|
||||
if (!RC || RC->isAllocatable())
|
||||
return RC;
|
||||
|
||||
const unsigned *SubClass = RC->getSubClassMask();
|
||||
for (unsigned Base = 0, BaseE = getNumRegClasses();
|
||||
Base < BaseE; Base += 32) {
|
||||
unsigned Idx = Base;
|
||||
for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
|
||||
unsigned Offset = CountTrailingZeros_32(Mask);
|
||||
const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
|
||||
if (SubRC->isAllocatable())
|
||||
return SubRC;
|
||||
Mask >>= Offset;
|
||||
Idx += Offset + 1;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/// getMinimalPhysRegClass - Returns the Register Class of a physical
|
||||
/// register of the given type, picking the most sub register class of
|
||||
/// the right type that contains this physreg.
|
||||
@ -71,6 +94,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
|
||||
/// registers for the specific register class.
|
||||
static void getAllocatableSetForRC(const MachineFunction &MF,
|
||||
const TargetRegisterClass *RC, BitVector &R){
|
||||
assert(RC->isAllocatable() && "invalid for nonallocatable sets");
|
||||
ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
|
||||
for (unsigned i = 0; i != Order.size(); ++i)
|
||||
R.set(Order[i]);
|
||||
@ -80,7 +104,10 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
|
||||
const TargetRegisterClass *RC) const {
|
||||
BitVector Allocatable(getNumRegs());
|
||||
if (RC) {
|
||||
getAllocatableSetForRC(MF, RC, Allocatable);
|
||||
// A register class with no allocatable subclass returns an empty set.
|
||||
const TargetRegisterClass *SubClass = getAllocatableClass(RC);
|
||||
if (SubClass)
|
||||
getAllocatableSetForRC(MF, SubClass, Allocatable);
|
||||
} else {
|
||||
for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
|
||||
E = regclass_end(); I != E; ++I)
|
||||
|
Loading…
Reference in New Issue
Block a user