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Also need to handle invalid imod values for CPS2p.

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rdar://problem/9186136


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-25 17:03:12 +00:00
parent 067e2e2adb
commit f14d5cf33a
2 changed files with 15 additions and 4 deletions
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15
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2965,8 +2965,10 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// opcodes which match the same real instruction. This is needed since there's
// no current handling of optional arguments. Fix here when a better handling
// of optional arguments is implemented.
if (Opcode == ARM::CPS3p) {
// Let's reject impossible imod values by returning false.
if (Opcode == ARM::CPS3p) { // M = 1
// Let's reject these impossible imod values by returning false:
// 1. (imod=0b01)
//
// AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
// invalid combination, so we just check for imod=0b00 here.
if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
@ -2977,13 +2979,18 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
NumOpsAdded = 3;
return true;
}
if (Opcode == ARM::CPS2p) {
if (Opcode == ARM::CPS2p) { // mode = 0, M = 0
// Let's reject these impossible imod values by returning false:
// 1. (imod=0b00,M=0)
// 2. (imod=0b01)
if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
return false;
MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags
NumOpsAdded = 2;
return true;
}
if (Opcode == ARM::CPS1p) {
if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1
MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
NumOpsAdded = 1;
return true;

4
test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# invalid imod value (0b01)
0xc0 0x67 0x4 0xf1